公开(公告)号：US4701780A

公开(公告)日：1987-10-20

申请号：US903200

申请日：1986-12-05

申请人： Kevin T. Hankins ,  Mark W. Michael ,  Jay D. Moser ,  Brian K. Rosier

发明人： Kevin T. Hankins ,  Mark W. Michael ,  Jay D. Moser ,  Brian K. Rosier

IPC分类号： H01L21/033 ,  H01L21/768 ,  H01L23/525 ,  H01L27/02 ,  H01L27/12 ,  H01L29/04 ,  H01L29/34

CPC分类号： H01L23/5252 ,  H01L21/033 ,  H01L21/76888 ,  H01L2924/0002

摘要： A method of forming an aligned vertical oxide fuse and emitter using a single mask. The mask includes an opening through which impurities are introduced into the base region through a first layer of insulation and which is subsequently used to form the emitter aperture through the first insulative layer. The thin fuse oxide is formed by non-selective oxidation after removal of the mask. Alternatively, the impurities may also be introduced through the emitter aperture or from doped thin fuse oxide after removal of the mask. The resulting integrated circuit includes at least three regions of oxidation of three thicknesses, in descending order, field oxide, device opening or gate oxide and fuse oxide.

摘要翻译： 使用单个掩模形成对准的垂直氧化物熔丝和发射体的方法。 掩模包括开口，通过该开口，杂质通过第一绝缘层被引入基底区域中，随后用于通过第一绝缘层形成发射器孔。 除去掩模之后，通过非选择性氧化形成薄熔丝氧化物。 或者，杂质也可以在除去掩模之后通过发射器孔或掺杂的薄熔丝氧化物引入。 所得到的集成电路包括三个厚度的氧化的至少三个区域，按降序，场氧化物，器件开路或栅极氧化物和熔丝氧化物。

公开(公告)号：US4635345A

公开(公告)日：1987-01-13

申请号：US711816

申请日：1985-03-14

申请人： Kevin T. Hankins ,  Mark W. Michael ,  Brian K. Rosier

发明人： Kevin T. Hankins ,  Mark W. Michael ,  Brian K. Rosier

IPC分类号： H01L21/033 ,  H01L23/525 ,  H01L21/20 ,  H01L21/479

CPC分类号： H01L23/5252 ,  H01L21/033 ,  H01L2924/0002 ,  Y10S438/981

摘要： A method of forming an aligned vertical oxide fuse and emitter using a single mask. The mask includes an opening through which impurities are introduced into the base region through a first layer of insulation and which is subsequently used to form the emitter aperture through the first insulative layer. The thin fuse oxide is formed by non-selective oxidation after removal of the mask. Alternatively, the impurities may also be introduced through the emitter aperture or from doped thin fuse oxide after removal of the mask. The resulting integrated circuit includes at least three regions of oxidation of three thicknesses, in descending order, field oxide, device opening or gate oxide and fuse oxide.

摘要翻译： 使用单个掩模形成对准的垂直氧化物熔丝和发射体的方法。 掩模包括开口，通过该开口，杂质通过第一绝缘层被引入基底区域中，随后用于通过第一绝缘层形成发射器孔。 除去掩模之后，通过非选择性氧化形成薄熔丝氧化物。 或者，杂质也可以在除去掩模之后通过发射器孔或掺杂的薄熔丝氧化物引入。 所得到的集成电路包括三个厚度的氧化的至少三个区域，按降序，场氧化物，器件开路或栅极氧化物和熔丝氧化物。

公开(公告)号：US07670938B2

公开(公告)日：2010-03-02

申请号：US11381219

申请日：2006-05-02

申请人： David D. Wu ,  Mark W. Michael

发明人： David D. Wu ,  Mark W. Michael

IPC分类号： H01L21/44

CPC分类号： H01L21/76819 ,  H01L21/76802 ,  H01L21/76834 ,  H01L29/7843

摘要： The present invention is directed to methods of forming contact openings. In one illustrative embodiment, the method includes forming a feature above a semiconducting substrate, forming a layer stack comprised of a plurality of layers of material above the feature, the layer stack having an original height, reducing the original height of the layer stack to thereby define a reduced height layer stack above the feature, forming an opening in the reduced height layer stack for a conductive member that will be electrically coupled to the feature and forming the conductive member in the opening in the reduced height layer stack.

摘要翻译： 本发明涉及形成接触开口的方法。 在一个说明性实施例中，该方法包括在半导体衬底上形成特征，形成由特征上方的多层材料构成的层叠层，层堆叠具有原始高度，从而降低层堆叠的原始高度 在所述特征之上限定减小的高度层堆叠，在所述减小的高度层堆叠中形成用于导电构件的开口，所述导电构件将电耦合到所述特征并且在所述还原高度层堆叠中的所述开口中形成所述导电构件。

公开(公告)号：US20090090969A1

公开(公告)日：2009-04-09

申请号：US11867743

申请日：2007-10-05

申请人： Ruigang Li ,  Jingrong Zhou ,  David Donggang Wu ,  Zhonghai Shi ,  James F. Buller ,  Mark W. Michael ,  Donna Michael ,  Akif Sultan ,  Fred Hause

发明人： Ruigang Li ,  Jingrong Zhou ,  David Donggang Wu ,  Zhonghai Shi ,  James F. Buller ,  Mark W. Michael ,  Donna Michael ,  Akif Sultan ,  Fred Hause

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A first bias charge is provided to first bias region at a first level of an electronic device, the first bias region directly underlying a first transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the first transistor is based upon the first bias charge. A second bias charge is provided to second bias region at the first level of an electronic device, the second bias region directly underlying a second transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the second transistor is based upon the second bias charge.

摘要翻译： 第一偏置电荷被提供给电子器件的第一电平处的第一偏置区域，直接位于第一晶体管下方的第一偏置区域具有与第一偏置区域电隔离的第二电平的沟道区域。 第一晶体管的电压阈值基于第一偏置电荷。 第二偏置电荷被提供给电子器件的第一电平处的第二偏置区域，第二偏置区域直接位于具有与第一偏置区域电隔离的第二电平的沟道区域的第二晶体管的正下方。 第二晶体管的电压阈值基于第二偏置电荷。

公开(公告)号：US06552776B1

公开(公告)日：2003-04-22

申请号：US09183176

申请日：1998-10-30

申请人： Derick J. Wristers ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Bradley T. Moore ,  Mark W. Michael

发明人： Derick J. Wristers ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Bradley T. Moore ,  Mark W. Michael

IPC分类号： G03B2754

CPC分类号： G03F7/70558 ,  G03F7/70191 ,  G03F7/706

摘要： A photolithographic system including a light filter that varies light intensity according to measured dimensional data that characterizes a lens error is disclosed. The light filter compensates for the lens error by reducing the light intensity of the image pattern as the lens error increases. In this manner, when the lens error causes focusing variations that result in enlarged portions of the image pattern, the light filter reduces the light intensity transmitted to the enlarged portions of the image pattern. This, in turn, reduces the rate in which regions of the photoresist layer beneath the enlarged portions of the image pattern are rendered soluble to a subsequent developer. As a result, after the photoresist layer is developed, linewidth variations that otherwise result from the lens error are reduced due to the light filter. Preferably, the light filter includes a light-absorbing film such as a semi-transparent layer such as calcium fluoride on a light-transmitting base such as a quartz plate, and the thickness of the light-absorbing film varies in accordance with the measured dimensional data to provide the desired variations in light intensity. The invention is particularly well-suited for patterning a photoresist layer that defines polysilicon gates of an integrated circuit device.

摘要翻译： 公开了一种光刻系统，其包括根据测量的尺寸数据来表征透镜误差来改变光强度的滤光器。 光滤波器通过降低镜头误差增大时图像图案的光强度来补偿镜头误差。 以这种方式，当透镜错误导致导致图像图案的放大部分的聚焦变化时，光过滤器降低传输到图像图案的扩大部分的光强度。 这又降低了图像图案的放大部分之下的光致抗蚀剂层的区域变得可溶于后续显影剂的速率。 结果，在光致抗蚀剂层显影之后，由于滤光器而导致透镜误差导致的线宽变化会降低。 优选地，光滤波器包括诸如石英板等透光基底上的诸如氟化钙的半透明层的光吸收膜，并且光吸收膜的厚度根据测量的尺寸而变化 数据以提供所需的光强度变化。 本发明特别适用于图案化限定集成电路器件的多晶硅栅极的光致抗蚀剂层。

公开(公告)号：US06323095B1

公开(公告)日：2001-11-27

申请号：US09489178

申请日：2000-01-21

申请人： Mark W. Michael ,  Jon D. Cheek ,  Robert Dawson

发明人： Mark W. Michael ,  Jon D. Cheek ,  Robert Dawson

IPC分类号： H01L21336

CPC分类号： H01L29/66492 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/8238 ,  H01L29/1083

摘要： A method for forming a semiconductor device is provided. The method includes providing a substrate having a gate formed thereon. A first doped region is formed in the substrate. The first doped region extends a first distance from the gate. A second doped region is formed in the substrate. The second doped region extends a second distance from the gate. The first distance is less than the second distance. A semiconductor device includes a substrate, isolation structures defined in the substrate, and a gate disposed on the substrate between adjacent isolation structures. A first doped region is defined in the substrate proximate the gate. The first doped region extends a first distance from the gate. A second doped region is defined in the substrate proximate the gate. The second doped region extends a second distance from the gate. The first distance is less than the first distance.

摘要翻译： 提供一种形成半导体器件的方法。 该方法包括提供其上形成有栅极的基板。 在衬底中形成第一掺杂区。 第一掺杂区域从栅极延伸第一距离。 在衬底中形成第二掺杂区。 第二掺杂区域从栅极延伸第二距离。 第一距离小于第二距离。 半导体器件包括衬底，限定在衬底中的隔离结构以及设置在相邻隔离结构之间的衬底上的栅极。 在靠近栅极的衬底中限定第一掺杂区域。 第一掺杂区域从栅极延伸第一距离。 在靠近栅极的衬底中限定第二掺杂区域。 第二掺杂区域从栅极延伸第二距离。 第一距离小于第一距离。

公开(公告)号：US6060345A

公开(公告)日：2000-05-09

申请号：US844924

申请日：1997-04-21

申请人： Frederick N. Hause ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Frederick N. Hause ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/823814

摘要： A method of making NMOS and PMOS devices with reduced masking steps is disclosed. The method includes providing a semiconductor substrate with a first active region of first conductivity type and a second active region of second conductivity type, forming a gate material over the first and second active regions, forming a first masking layer over the gate material, etching the gate material using the first masking layer as an etch mask to form a first gate over the first active region and a second gate over the second active region, implanting a dopant of second conductivity type into the first and second active regions using the first masking layer as an implant mask, forming a second masking layer that covers the first active region and includes an opening above the second active region, and implanting a dopant of first conductivity type into the second active region using the first and second masking layers as an implant mask. Advantageously, the dopant of first conductivity type counterdopes the dopant of second conductivity type in the second active region, thereby providing source and drain regions of second conductivity type in the first active region and source and drain regions of first conductivity type in the second active region with a single masking step and without subjecting either gate to dopants of first and second conductivity type.

摘要翻译： 公开了一种制造具有减小的掩蔽步骤的NMOS和PMOS器件的方法。 该方法包括提供具有第一导电类型的第一有源区和第二导电类型的第二有源区的半导体衬底，在第一和第二有源区上形成栅极材料，在栅极材料上形成第一掩模层， 栅极材料，使用第一掩模层作为蚀刻掩模，以在第一有源区上形成第一栅极，在第二有源区上形成第二栅极，使用第一掩模层将第二导电类型的掺杂剂注入到第一和第二有源区中 作为注入掩模，形成覆盖第一有源区并且包括在第二有源区上方的开口的第二掩模层，以及使用第一和第二掩模层作为注入掩模将第一导电类型的掺杂剂注入到第二有源区中 。 有利地，第一导电类型的掺杂剂在第二有源区域中抵消第二导电类型的掺杂剂，从而在第一有源区域中提供第二导电类型的源极和漏极区域，并且在第二有源区域中提供第一导电类型的源极和漏极区域 具有单个掩蔽步骤，并且不对任一个栅极施加第一和第二导电类型的掺杂剂。

公开(公告)号：US5962894A

公开(公告)日：1999-10-05

申请号：US30052

申请日：1998-02-24

申请人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21/336 ,  H01L29/417 ,  H01L29/423 ,  H01L29/76 ,  H01L31/062

CPC分类号： H01L29/41775 ,  H01L29/66621 ,  H01L29/78

摘要： An IGFET with a gate electrode and metal spacers in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, metal spacers adjacent to the sidewalls and the bottom surface, a gate insulator on the bottom surface between the metal spacers, protective insulators on the metal spacers, a gate electrode on the gate insulator and protective insulators, and a source and drain adjacent to the bottom surface. A method of forming the IGFET includes implanting a doped layer into the substrate, etching completely through the doped layer and partially through the substrate to form the trench and split the doped layer into source and drain regions, applying a high-temperature anneal to diffuse the source and drain regions beneath the bottom surface, depositing a blanket layer of conductive metal over the substrate and applying an anisotropic etch to form the metal spacers, depositing a continuous insulative layer over the substrate to provide the gate insulator and the protective insulators, depositing a blanket layer of gate electrode material over the substrate, and polishing the gate electrode material so that the gate electrode is substantially aligned with a top surface of the substrate. Advantageously, the channel length is significantly smaller than the trench length, and the metal spacers reduce the parasitic resistance of lightly doped source and drain regions.

摘要翻译： 公开了具有沟槽中的栅电极和金属间隔物的IGFET。 IGFET包括具有相对的侧壁和半导体衬底中的底表面的沟槽，与侧壁和底表面相邻的金属间隔物，位于金属间隔物之间​​的底表面上的栅极绝缘体，金属间隔物上的保护绝缘体，栅电极 在栅极绝缘体和保护绝缘体上，以及与底表面相邻的源极和漏极。 形成IGFET的方法包括将掺杂层注入到衬底中，完全通过掺杂层蚀刻并部分地穿过衬底以形成沟槽并将掺杂层分裂成源极和漏极区域，施加高温退火以扩散 在底表面下方的源极和漏极区域，在衬底上沉积导电金属的覆盖层，并施加各向异性蚀刻以形成金属间隔物，在衬底上沉积连续的绝缘层以提供栅极绝缘体和保护绝缘体， 覆盖衬底上的栅电极材料层，并且对栅电极材料进行抛光，使得栅电极基本上与衬底的顶表面对准。 有利地，沟道长度显着小于沟槽长度，并且金属间隔物减少了轻掺杂源极和漏极区域的寄生电阻。

公开(公告)号：US5930634A

公开(公告)日：1999-07-27

申请号：US844927

申请日：1997-04-21

申请人： Frederick N. Hause ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Frederick N. Hause ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/66575 ,  H01L21/28035 ,  H01L21/28052 ,  H01L29/42376 ,  H01L29/4925 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of making an IGFET with a multilevel gate that includes upper and lower gate levels is disclosed. The method includes providing a semiconductor substrate with an active region, forming a gate insulator on the active region, forming a first gate material with a thickness of at most 1000 angstroms on the gate inslator and over the active region, forming a first photoresist layer over the first gate material, irradiating the first photoresist layer with a first image pattern and removing irradiated portions of the first photoresist layer to provide openings above the active region, etching the first gate material through the openings in the first photoresist layer using the first photoresist layer as an etch mask for a portion of the first gate material that forms a lower gate level, removing the first photoresist layer, forming an upper gate level on the lower gate level after removing the first photoresist layer, and forming a source and drain in the active region. Advantageously, the first photoresist layer can be ultra-thin to enhance the accuracy in which the image pattern is replicated, thereby reducing variations in channel length and device performance.

摘要翻译： 公开了一种制造具有包括上下栅极电平的多电平栅极的IGFET的方法。 该方法包括提供具有有源区的半导体衬底，在有源区上形成栅极绝缘体，在栅极绝缘体上并在有源区上形成厚度至多为1000埃的第一栅极材料，形成第一光致抗蚀剂层 第一栅极材料，用第一图案图案照射第一光致抗蚀剂层，并去除第一光致抗蚀剂层的照射部分以在有源区上方提供开口，使用第一光致抗蚀剂层蚀刻通过第一光致抗蚀剂层中的开口的第一栅极材料 作为用于形成下栅极电平的第一栅极材料的一部分的蚀刻掩模，去除第一光致抗蚀剂层，在去除第一光致抗蚀剂层之后在下栅极电平上形成上栅极电平，并在其中形成源极和漏极 活跃区域。 有利地，第一光致抗蚀剂层可以是超薄的，以提高复制图像图案的精度，从而减少通道长度和器件性能的变化。

公开(公告)号：US5894168A

公开(公告)日：1999-04-13

申请号：US947521

申请日：1997-10-02

申请人： Mark W. Michael ,  Robert Dawson ,  Fred N. Hause ,  Basab Bandyopadhyay ,  H. Jim Fulford, Jr. ,  William S. Brennan

发明人： Mark W. Michael ,  Robert Dawson ,  Fred N. Hause ,  Basab Bandyopadhyay ,  H. Jim Fulford, Jr. ,  William S. Brennan

IPC分类号： H01L21/3105 ,  H01L21/768 ,  H01L23/528 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76819 ,  H01L21/31053 ,  H01L23/528 ,  H01L2924/0002

摘要： A photolithography mask derivation process is provided for improving the overall planarity of interlevel dielectric deposited upon conductors formed by the derived photolithography mask. The photolithography mask is derived such that non-operational conductors are spaced a minimum distance from each other and from operational conductors to present a regular spaced arrangement of conductors upon which a dielectric layer can be deposited and readily planarized using, for example, chemical-mechanical polishing techniques. The resulting interlevel dielectric upper surface is globally planarized to an even elevational level across the entire semiconductor topography. The operational conductors are dissimilar from non-operational conductors in that the operational conductors are connected within a circuit path of an operational integrated circuit. Non-operational conductors are not connected within the integrated circuit path and generally are floating or are connected to a power supply. The non-operational conductors thereby do not contribute to the integrated circuit functionality other than to provide structural planarity to the overlying interlevel dielectric. The mask derivation process is applicable to either a metal interconnect photolithography mask or a polysilicon interconnect photolithography mask.

摘要翻译： 提供了一种光刻掩模衍生方法，用于改善沉积在由衍生的光刻掩模形成的导体上的层间电介质的整体平面性。 衍生出光刻掩模，使得非操作导体彼此间隔开最小距离和与操作导体间隔开的规则间隔排列的导体，其上可使用例如化学机械的电介质层沉积并容易地平坦化 抛光技术。 所得的层间电介质上表面在整个半导体形貌上被全局平坦化到均匀的高度。 操作导体与非操作导体不相似，因为操作导体连接在可操作的集成电路的电路中。 非操作导体不在集成电路路径内连接，并且通常浮动或连接到电源。 因此，非操作导体对集成电路功能没有贡献，而不是为覆盖的层间电介质提供结构平面性。 掩模推导方法适用于金属互连光刻掩模或多晶硅互连光刻掩模。