公开(公告)号：US07279413B2

公开(公告)日：2007-10-09

申请号：US10869658

申请日：2004-06-16

申请人： Dae-Gyu Park ,  Oleg G. Gluschenkov ,  Michael A. Gribelyuk ,  Kwong Hon Wong

发明人： Dae-Gyu Park ,  Oleg G. Gluschenkov ,  Michael A. Gribelyuk ,  Kwong Hon Wong

IPC分类号： H01L21/4763

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28229 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

摘要： The present invention provides a method for depositing a dielectric stack comprising forming a dielectric layer atop a substrate, the dielectric layer comprising at least oxygen and silicon atoms; forming a layer of metal atoms atop the dielectric layer within a non-oxidizing atmosphere, wherein the layer of metal atoms has a thickness of less than about 15 Å; forming an oxygen diffusion barrier atop the layer of metal atoms, wherein the non-oxidizing atmosphere is maintained; forming a gate conductor atop the oxygen diffusion barrier; and annealing the layer of metal atoms and the dielectric layer, wherein the layer of metal atoms reacts with the dielectric layer to provide a continuous metal oxide layer having a dielectric constant ranging from about 25 to about 30 and a thickness less than about 15 Å.

摘要翻译： 本发明提供一种用于沉积电介质堆叠的方法，包括在衬底顶部形成电介质层，所述电介质层至少包含氧和硅原子; 在非氧化性气氛中在所述电介质层的顶部形成金属原子层，其中所述金属原子层具有小于约的厚度; 在金属原子层的上方形成氧扩散阻挡层，其中保持非氧化性气氛; 在氧扩散阻挡层上形成栅极导体; 以及退火所述金属原子层和所述介电层，其中所述金属原子层与所述电介质层反应以提供介电常数范围为约25至约30且厚度小于约的连续金属氧化物层。

公开(公告)号：US20060237803A1

公开(公告)日：2006-10-26

申请号：US10907935

申请日：2005-04-21

申请人： Wenjuan Zhu ,  Michael Chudzik ,  Oleg Gluschenkov ,  Dae-Gyu Park ,  Akihisa Sekiguchi

发明人： Wenjuan Zhu ,  Michael Chudzik ,  Oleg Gluschenkov ,  Dae-Gyu Park ,  Akihisa Sekiguchi

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/28185 ,  H01L21/28097 ,  H01L21/28229 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517

摘要： A semiconductor structure and method of forming the same, comprising forming a uniform buffer layer of diffusion-controlling stable material on top of a base gate dielectric layer, and then forming a uniform layer which contains a source of transitional metal atoms, and then annealing the structure to diffuse the transitional metal atoms from their source through the diffusion-controlling material and into the base gate dielectric layer.

摘要翻译： 一种半导体结构及其制造方法，包括在基极电介质层的顶部形成扩散控制稳定材料的均匀缓冲层，然后形成含有过渡金属原子源的均匀层，然后退火 结构将过渡金属原子从其源极扩散通过扩散控制材料并进入基极栅极电介质层。

公开(公告)号：US20050280099A1

公开(公告)日：2005-12-22

申请号：US10710063

申请日：2004-06-16

申请人： Dae-Gyu Park ,  Cyril Cabral ,  Oleg Gluschenkov ,  Hyungjun Kim

发明人： Dae-Gyu Park ,  Cyril Cabral ,  Oleg Gluschenkov ,  Hyungjun Kim

IPC分类号： H01L21/8238 ,  H01L29/76

CPC分类号： H01L21/823842 ,  H01L21/823857 ,  Y10S257/90 ,  Y10S438/942

摘要： An integrated circuit is provided including an FET gate structure formed on a substrate. This structure includes a gate dielectric on the substrate, and a metal nitride layer overlying the gate dielectric and in contact therewith. This metal nitride layer is characterized as MNx, where M is one of W, Re, Zr, and Hf, and x is in the range of about 0.7 to about 1.5. Preferably the layer is of WNx, and x is about 0.9. Varying the nitrogen concentration in the nitride layer permits integration of different FET characteristics on the same chip. In particular, varying x in the WNx layer permits adjustment of the threshold voltage in the different FETs. The polysilicon depletion effect is substantially reduced, and the gate structure can be made thermally stable up to about 1000° C.

摘要翻译： 提供了一种集成电路，其包括形成在衬底上的FET栅极结构。 该结构包括衬底上的栅极电介质和覆盖栅极电介质并与其接触的金属氮化物层。 该金属氮化物层的特征在于MN x，其中M是W，Re，Zr和Hf之一，x在约0.7至约1.5的范围内。 优选地，该层为W N x X，x为约0.9。 改变氮化物层中的氮浓度允许在同一芯片上集成不同的FET特性。 特别地，在WN 层中改变x允许调节不同FET中的阈值电压。 多晶硅耗尽效应显着降低，并且栅极结构可以在高达约1000℃下热稳定。

公开(公告)号：US20050196932A1

公开(公告)日：2005-09-08

申请号：US11124324

申请日：2005-05-06

申请人： Ramachandra Divakaruni ,  Jack Mandelman ,  Dae-Gyu Park

发明人： Ramachandra Divakaruni ,  Jack Mandelman ,  Dae-Gyu Park

IPC分类号： H01L21/20 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10864

摘要： The present invention comprises a method including the steps of providing a substrate; forming a trench in the substrate; forming a buried plate in the substrate about the trench; depositing a dielectric layer within the trench; and then depositing a P-type metal atop the dielectric layer, where the dielectric layer is positioned between the P-type metal and the buried plate. Another aspect of the present invention provides a trench capacitor where said trench capacitor comprises a trench formed in a substrate, a buried plate formed in the substrate about the trench; a node dielectric; and a P-type metal liner deposited within the trench, where the P-type metal liner is separated from the buried plate by the node dielectric. A P-type metal is defined as a metal having a work function close to the Si valence band, approximately equal to 5.1 eV.

摘要翻译： 本发明包括一种方法，包括提供基底的步骤; 在衬底中形成沟槽; 在沟槽周围形成衬底; 在沟槽内沉积介电层; 然后在电介质层的顶部沉积P型金属，其中电介质层位于P型金属和掩埋板之间。 本发明的另一方面提供一种沟槽电容器，其中所述沟槽电容器包括形成在衬底中的沟槽，在衬底周围形成的掩埋板围绕沟槽; 节点电介质; 以及沉积在沟槽内的P型金属衬垫，其中P型金属衬垫通过节点电介质与掩埋板分离。 P型金属被定义为具有接近于Si价带的功函数的金属，大约等于5.1eV。

公开(公告)号：US06579767B2

公开(公告)日：2003-06-17

申请号：US09727583

申请日：2000-12-04

申请人： Dae-Gyu Park ,  Se-Aug Jang ,  Jeong-Youb Lee ,  Hung-Jae Cho ,  Jung-Ho Kim

发明人： Dae-Gyu Park ,  Se-Aug Jang ,  Jeong-Youb Lee ,  Hung-Jae Cho ,  Jung-Ho Kim

IPC分类号： H01L29227

CPC分类号： H01L29/517 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/31155 ,  H01L21/3162 ,  H01L21/31662 ,  H01L29/513

摘要： A method for forming a gate structure begins by preparing a semiconductor substrate provided with an isolation region formed therein. A thin SiO2 layer is thermally grown on top of the semiconductor device by using a wet H2/O2 or a dry O2. And then, an aluminum oxide layer is formed on top of the semiconductor substrate with doping a dopant in situ. A conductive layer is formed on top of the Al2O3 layer. Finally, the conductive layer and the Al2O3 layer are patterned into the gate structure. The dopant is a material selected from a group consisting of Si, Zr, Hf, Nb or the like.

摘要翻译： 用于形成栅极结构的方法开始于制备其中形成有隔离区域的半导体衬底。 通过使用湿的H2 / O2或干燥的O 2，在半导体器件的顶部上热生长薄的SiO 2层。 然后，通过原位掺杂掺杂剂在半导体衬底的顶部上形成氧化铝层。 导电层形成在Al2O3层的顶部。 最后，将导电层和Al 2 O 3层图案化成栅极结构。 掺杂剂是选自Si，Zr，Hf，Nb等的材料。

公开(公告)号：US06524918B2

公开(公告)日：2003-02-25

申请号：US09739292

申请日：2000-12-19

申请人： Dae-Gyu Park ,  Se-Aug Jang ,  Jeong-Youb Lee

发明人： Dae-Gyu Park ,  Se-Aug Jang ,  Jeong-Youb Lee

IPC分类号： H01L21336

CPC分类号： H01L21/28185 ,  H01L21/02145 ,  H01L21/02271 ,  H01L21/02321 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/28194 ,  H01L21/28211 ,  H01L21/3115 ,  H01L21/31616 ,  H01L29/513 ,  H01L29/517

摘要： A method for forming a gate structure begins by preparing a semiconductor substrate provided with an isolation region formed therein. An aluminum oxide (Al2O3) layer is deposited on top of the semiconductor substrate and then, silicon ions plasma doping is carried out. Thereafter, the Al2O3 layer doped with silicon ions is annealed in the presence of oxygen gas or nitrous oxygen to remove a metallic vacancy in the Al2O3 layer. Subsequently, a conductive layer is formed on top of the Al2O3 layer. Finally, the conductive layer is patterned into the gate structure.

摘要翻译： 用于形成栅极结构的方法开始于制备其中形成有隔离区域的半导体衬底。 在半导体衬底的顶部上沉积氧化铝（Al2O3）层，然后进行硅离子等离子体掺杂。 此后，在氧气或亚硝态氧的存在下对掺有硅离子的Al 2 O 3层进行退火以除去Al 2 O 3层中的金属空位。 随后，在Al 2 O 3层的顶部上形成导电层。 最后，将导电层图案化成栅极结构。

公开(公告)号：US06511875B2

公开(公告)日：2003-01-28

申请号：US09883188

申请日：2001-06-19

申请人： Dae-Gyu Park ,  Heung-Jae Cho

发明人： Dae-Gyu Park ,  Heung-Jae Cho

IPC分类号： H01L218242

CPC分类号： H01L29/517 ,  C23C16/405 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/31604 ,  H01L29/66545

摘要： A method for forming a gate structure beginning with a semiconductor substrate provided with an isolation region formed therein. An HfO2 layer and a conductive layer are formed on the semiconductor substrate, subsequently. The conductive layer and the HfO2 layer are patterned into the gate structure. By utilizing an HfO2 layer as a gate dielectric, an effective K of the gate dielectric can be controlled to within 18 to 25. In addition, by employing a CVD method for forming the HfO2 layer, it is possible to obtain a high K gate dielectric with excellent leakage current characteristic as well as a low interface state with both a gate electrode and a semiconductor substrate.

摘要翻译： 一种形成栅极结构的方法，从形成有隔离区域的半导体衬底开始。 随后在半导体衬底上形成HfO 2层和导电层。 将导电层和HfO 2层图案化成栅极结构。 通过使用HfO 2层作为栅极电介质，可以将栅极电介质的有效K控制在18〜25的范围内。此外，通过采用CVD法形成HfO 2层，可以获得高K栅极电介质 具有优异的漏电流特性以及与栅电极和半导体衬底两者的低接口状态。

公开(公告)号：US06355548B1

公开(公告)日：2002-03-12

申请号：US09722465

申请日：2000-11-28

申请人： Dae-Gyu Park

发明人： Dae-Gyu Park

IPC分类号： H01L213205

CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L21/31683 ,  H01L21/318 ,  H01L29/518

摘要： A method for forming a gate structure begins by preparing a semiconductor substrate provided with an isolation region formed therein. An AlN layer is formed on top of the semiconductor substrate and annealed in the presence of oxygen gas to convert into an Al2O3 layer. Thereafter, a conductive layer is formed on top of the Al2O3 layer. Finally, the conductive layer and the Al2O3 layer are patterned into the gate structure.

摘要翻译： 用于形成栅极结构的方法开始于制备其中形成有隔离区域的半导体衬底。 在半导体衬底的顶部上形成AlN层，并在氧气存在下退火以转化为Al 2 O 3层。 此后，在Al 2 O 3层的顶部上形成导电层。 最后，将导电层和Al 2 O 3层图案化成栅极结构。