公开(公告)号：US20180123032A1

公开(公告)日：2018-05-03

申请号：US15856202

申请日：2017-12-28

Applicant: Everspin Technologies, Inc.

Inventor： Sanjeev Aggarwal ,  Kerry Nagel ,  Jason Janesky

IPC: H01L43/12 ,  G11C11/16 ,  H01L43/10 ,  H01L43/02 ,  H01L43/08

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. For example, an exemplary method of manufacturing a magnetoresistive device includes etching through a second electrode, second dielectric layer and free magnetic layer to provide a sidewall of (i) an unpinned synthetic antiferromagnetic structure, (ii) a second dielectric layer and (iii) a free magnetic layer; thereafter, forming an encapsulation material on the sidewall of the unpinned synthetic antiferromagnetic structure, second dielectric layer and free magnetic layer, and after forming the encapsulation material, etching through a first dielectric layer.

公开(公告)号：US09722174B1

公开(公告)日：2017-08-01

申请号：US14593445

申请日：2015-01-09

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Kerry Joseph Nagel ,  Sanjeev Aggarwal

IPC: H01L43/12 ,  H01L21/00 ,  H01L43/02 ,  H01L43/08

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L43/08

Abstract: By manufacturing magnetoresistive devices using low-k dielectric materials as the inter-layer dielectrics and higher-k dielectric materials for hard masks and encapsulation, the overall dielectric constant characteristics of the magnetoresistive devices can be kept lower, thereby decreasing capacitance and allowing for higher speed operations. Elimination or reduction of residual higher-k dielectric material through stripping or other processes minimizes “islands” of higher-k dielectric material that can detract from overall dielectric constant performance. One or more masking and one or more etching steps can be used to form the devices either with or without the additional stripping of the higher-k material.

公开(公告)号：US20170125663A1

公开(公告)日：2017-05-04

申请号：US15337123

申请日：2016-10-28

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Joseph Nagel ,  Wenchin Lin ,  Sarin A. Deshpande ,  Jijun Sun ,  Sanjeev Aggarwal ,  Chaitanya Mudivarthi

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  H01L43/10

CPC classification number: H01L43/12 ,  G11C11/161 ,  G11C2211/5615 ,  H01L43/08

Abstract: A method of manufacturing a magnetoresistive stack/structure comprising etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer; depositing a first encapsulation layer on the sidewalls of the second magnetic region and over the dielectric layer; etching the first encapsulation layer which is disposed over the exposed surface of the dielectric layer. The method further includes (a) depositing a second encapsulation layer: (i) on the first encapsulation layer disposed on the sidewalls of the second magnetic region and (ii) over the exposed surface of the dielectric layer and (b) depositing a third encapsulation layer: (i) on the second encapsulation layer which is on the first encapsulation layer and the exposed surface of the dielectric layer. The method also includes etching the remaining layers of the stack/structure (via one or more etch processes).

公开(公告)号：US20170117462A1

公开(公告)日：2017-04-27

申请号：US15399971

申请日：2017-01-06

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Joseph Nagel ,  Kenneth Smith ,  Moazzem Hossain ,  Sanjeev Aggarwal

IPC: H01L43/12 ,  H01L21/768 ,  H01L27/22

CPC classification number: H01L43/12 ,  H01L21/28568 ,  H01L21/32133 ,  H01L21/76819 ,  H01L21/7684 ,  H01L21/76877 ,  H01L27/222 ,  H01L27/226 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08

Abstract: A method of manufacturing one or more interconnects to magnetoresistive structure comprising (i) depositing a first conductive material in a via; (2) etching the first conductive material wherein, after etching the first conductive material a portion of the first conductive material remains in the via, (3) partially filling the via by depositing a second conductive material in the via and directly on the first conductive material in the via; (4) depositing a first electrode material in the via and directly on the second conductive material in the via; (5) polishing a first surface of the first electrode material wherein, after polishing, the first electrode material is (i) on the second conductive material in the via and (ii) over the portion of the first conductive material remaining in the via; and (6) forming a magnetoresistive structure over the first electrode material.

公开(公告)号：US09553260B2

公开(公告)日：2017-01-24

申请号：US14704915

申请日：2015-05-05

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Joseph Nagel ,  Kenneth Smith ,  Moazzem Hossain ,  Sanjeev Aggarwal

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L27/22 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/285

CPC classification number: H01L43/12 ,  H01L21/28568 ,  H01L21/32133 ,  H01L21/76819 ,  H01L21/7684 ,  H01L21/76877 ,  H01L27/222 ,  H01L27/226 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08

Abstract: A conductive via disposed beneath a magnetic device and aligned therewith. In certain embodiments, an electrode formed on the conductive via may be polished to eliminate step functions or seams originating at the conductive via from propagating up through the various deposited layers. This integration approach allows for improved scaling of the MRAM devices to, for example, a 45 nanometer node.

Abstract translation: 导电通孔，其设置在磁性装置的下方并与其对准。 在某些实施例中，形成在导电通孔上的电极可以被抛光以消除起始于导电通孔的步骤功能或接缝，以向上传播通过各种沉积层。 该集成方法允许将MRAM设备改进为例如45纳米节点。

公开(公告)号：US20160372517A1

公开(公告)日：2016-12-22

申请号：US15249559

申请日：2016-08-29

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Joseph Nagel ,  Sanjeev Aggarwal ,  Moazzem Hossain ,  Nicholas Rizzo

IPC: H01L27/22 ,  H01L43/12 ,  G11C11/16 ,  H01L43/08 ,  H01L43/02

CPC classification number: H01L27/222 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A layer of silicon nitride above the bottom electrode and on the sidewalls of the magnetoresistive stack serves as an insulator and an etch stop during manufacturing of a magnetoresistive device. Non-selective chemical mechanical polishing removes any silicon nitride overlying a top electrode for the device along with silicon dioxide used for encapsulation. Later etching operations corresponding to formation of a via to reach the top electrode use selective etching chemistries that remove silicon dioxide to access the top electrode, but do not remove silicon nitride. Thus, the silicon nitride acts as an etch stop, and, in the resulting device, provides an insulating layer that prevents unwanted short circuits between the via and the bottom electrode and between the via and the sidewalls of the magnetoresistive device stack.

公开(公告)号：US20160027998A1

公开(公告)日：2016-01-28

申请号：US14340209

申请日：2014-07-24

Applicant: Everspin Technologies, Inc.

Inventor： Chaitanya Mudivarthi ,  Sanjeev Aggarwal

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/02

CPC classification number: H01L43/12 ,  H01L43/02 ,  H01L43/08

Abstract: A via underlying a magnetoresistive device is formed to include a lower portion that includes a first material and an upper portion that includes a second material, where the second material is part of the material making up the bottom electrode of the magnetoresistive device. The via is formed by partially filling a via hole with the first material and then filling the remaining portion of the via hole when a layer of the second material is deposited to form the basis for the bottom electrode. The layer of second material is polished to provide a planar surface on which to form the magnetoresistive stack and top electrode. After forming the magnetoresistive stack and top electrode, the layer of second material is etched to form the bottom electrode. Such a via allows the magnetoresistive stack to be formed directly over the via, thereby reducing the area required for each device and increasing density in applications such as MRAMs.

Abstract translation: 形成在磁阻器件下方的通孔形成为包括下部，其包括第一材料和包括第二材料的上部，其中第二材料是组成磁阻器件的底部电极的材料的一部分。 所述通孔是通过用第一材料部分地填充通孔而形成的，然后当沉积第二材料的一层以形成底部电极的基底时，填充通孔的剩余部分。 第二材料层被抛光以提供平面，在其上形成磁阻堆叠和顶电极。 在形成磁阻堆叠和顶电极之后，蚀刻第二材料层以形成底电极。 这样的通孔允许直接在通孔上形成磁阻堆叠，从而减少每个器件所需的面积，并增加诸如MRAM之类的应用中的密度。

公开(公告)号：US20150318465A1

公开(公告)日：2015-11-05

申请号：US14797172

申请日：2015-07-12

Applicant: Everspin Technologies, Inc.

Inventor： Sanjeev Aggarwal ,  Kerry Nagel ,  Jason Janesky

IPC: H01L43/02 ,  H01L43/12 ,  H01L43/08

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least an encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes.

Abstract translation: 具有两个电介质层的磁阻结构及其制造方法包括位于两个电介质层之间的自由磁性层。 制造方法包括至少两个蚀刻工艺和至少一个介于其间的封装工艺，其中在蚀刻工艺之间形成在部分形成的磁阻堆叠的侧壁上的封装。

公开(公告)号：US20150079699A1

公开(公告)日：2015-03-19

申请号：US14532797

申请日：2014-11-04

Applicant: Everspin Technologies, Inc.

Inventor： Sarin Deshpande ,  Sanjeev Aggarwal ,  Kerry Nagel

IPC: H01L43/12

CPC classification number: G11B5/127 ,  G11C11/161 ,  H01L43/12 ,  Y10T29/49052

Abstract: A method of manufacturing a magnetoresistive-based device includes a metal hard mask that is inert to a top electrode etch chemistry and that has low sputter yield during a magnetic stack sputter. The metal hard mask is patterned by the photo resist and the photo mask is then stripped and the top electrode (overlying magnetic materials of the magnetoresistive-based device) is patterned by the metal hard mask.

Abstract translation: 制造基于磁阻的器件的方法包括对顶部电极蚀刻化学物质是惰性的并且在磁堆栈溅射期间具有低的溅射产率的金属硬掩模。 金属硬掩模由光致抗蚀剂构图，然后剥离光掩模，并且通过金属硬掩模对顶部电极（基于磁阻的装置的覆盖磁性材料）进行图案化。

公开(公告)号：US20140287536A1

公开(公告)日：2014-09-25

申请号：US14283413

申请日：2014-05-21

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Nagel ,  Sarin Deshpande ,  Moazzem Hossain ,  Sanjeev Aggarwal

IPC: H01L43/12 ,  H01L21/768

CPC classification number: H01L43/12 ,  H01L21/76883 ,  H01L21/76898 ,  H01L23/544 ,  H01L27/222 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is provided for forming a first via with an electrically conductive material, for example, copper, that is formed over and coupled to a conductive landing pad of an MRAM array. A sputter step is performed to lower the surface of the first via below that of a surrounding dielectric material. This recess is repeated in subsequent processing steps, providing alignment marks for the formation of a magnetic tunnel junction. The magnetic tunnel junction may be offset from the first via, and a second via being formed above the magnetic tunnel junction and to a conductive layer.

Abstract translation: 提供了一种用于形成第一通孔的方法，其中导电材料例如铜形成在MRAM阵列的导电着陆焊盘上并耦合到MRAM阵列的导电着陆焊盘。 执行溅射步骤以将第一通孔的表面降低到低于周围电介质材料的表面。 在随后的处理步骤中重复该凹槽，提供用于形成磁性隧道结的对准标记。 磁性隧道结可以偏离第一通孔，并且第二通孔形成在磁性隧道结上方和导电层上。