公开(公告)号：US09691664B1

公开(公告)日：2017-06-27

申请号：US15170126

申请日：2016-06-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Chanro Park ,  Hoon Kim ,  Ruilong Xie

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/311 ,  H01L27/088 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L21/823431 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/31111 ,  H01L21/823462 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/42364 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of forming a thick oxide layer over fins for EG devices and a thinner oxide layer over fins for SG devices on the same substrate and the resulting device are provided. Embodiments include forming a first set of fins over a first portion of a Si substrate; forming a second set of fins over a second portion of the Si substrate spaced from the first portion; forming an iRAD SiO2 layer over the first and second sets of fins; forming a polysilicon layer over the iRAD SiO2 layer over the first set of fins; forming a radical SiO2 layer over the iRAD SiO2 layer over the second set of fins and over the polysilicon layer; forming a mask over the radical SiO2 layer over the second set of fins; removing the polysilicon layer; and removing the mask and the iRAD SiO2 layer from the first set of fins.

公开(公告)号：US20170053835A1

公开(公告)日：2017-02-23

申请号：US14828652

申请日：2015-08-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Chanro Park ,  Ruilong Xie ,  Hoon Kim

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L27/0924

Abstract: One illustrative method disclosed herein includes, among other things, performing a first trench etching process to define an upper portion of a first fin for an NFET device and an upper portion of a second fin for a PFET device, performing a first conformal deposition process to form a conformal etch stop layer around the upper portion of both the first and second fins, with the NFET device masked, performing a second trench etching process to define a lower portion of the second fin, and performing a second conformal deposition process to form a conformal protection layer adjacent the upper portion of the second fin and on sidewalls of the lower portion of the second fin.

Abstract translation: 本文中公开的一种说明性方法包括执行第一沟槽蚀刻工艺以限定NFET器件的第一鳍片的上部分和用于PFET器件的第二鳍片的上部，执行第一共形沉积工艺 在所述第一和第二鳍片的上部周围形成保形蚀刻停止层，其中所述NFET器件被掩蔽，执行第二沟槽蚀刻工艺以限定所述第二鳍片的下部分，以及执行第二共形沉积工艺以形成 保形层邻近第二鳍片的上部并且在第二鳍片的下部的侧壁上。

公开(公告)号：US09548249B2

公开(公告)日：2017-01-17

申请号：US14633544

申请日：2015-02-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Catherine B. Labelle

IPC: H01L21/8234 ,  H01L21/762 ,  H01L21/308

CPC classification number: H01L21/823431 ,  H01L21/3083 ,  H01L21/76224 ,  H01L21/823481

Abstract: A method includes forming a plurality of fins above a substrate. A first mask layer is formed above a first subset of the fins. First portions of the fins in the first subset exposed by a first opening in the first mask layer are removed to define, for each of the fins, a first fin segment and a second fin segment, each having a cut end surface. A first liner layer is formed on at least the cut end surface of the first fin segment for each of the fins in the first subset. A second mask layer having a second opening is formed above a second subset of the plurality of fins. An etching process removes second portions of the second subset of fins exposed by the second opening. The first liner layer protects the cut end surface of at least the first fin segment during the removing.

Abstract translation: 一种方法包括在衬底上形成多个翅片。 第一掩模层形成在翅片的第一子集上方。 移除在第一掩模层中由第一开口暴露的第一子集中的翅片的第一部分，以为每个翅片限定每个具有切割端面的第一翅片段和第二翅片段。 在第一子集中的每个鳍​​片的至少第一鳍片段的切割端表面上形成第一衬里层。 具有第二开口的第二掩模层形成在多个翅片的第二子集之上。 蚀刻工艺除去由第二开口暴露的第二翅片子集的第二部分。 在移除期间，第一衬里层保护至少第一鳍段的切割端表面。

公开(公告)号：US20160190263A1

公开(公告)日：2016-06-30

申请号：US15053640

申请日：2016-02-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  William J. Taylor ,  Min Gyu Sung

IPC: H01L29/417

CPC classification number: H01L29/41783 ,  H01L21/28008 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823828 ,  H01L21/823871 ,  H01L27/088 ,  H01L29/0653

Abstract: A device includes an isolation region that defines an active region in a semiconducting substrate and a gate structure, wherein the gate structure has an axial length in a long axis direction thereof such that a first portion of the gate structure is positioned above the active region and a second portion of the gate structure is positioned above the isolation region. Additionally, a gate cap layer is positioned above the gate structure, wherein a first portion of the gate cap layer that is positioned above the first portion of the gate structure is thicker than a second portion of the gate cap layer that is positioned above the second portion of the gate structure.

Abstract translation: 一种器件包括限定半导体衬底和栅极结构中的有源区的隔离区，其中栅极结构在其长轴方向上具有轴向长度，使得栅极结构的第一部分位于有源区上方，并且 栅极结构的第二部分位于隔离区的上方。 另外，栅极覆盖层位于栅极结构的上方，其中位于栅极结构的第一部分之上的栅极覆盖层的第一部分比位于栅极结构的第二部分之上的栅极覆盖层的第二部分更厚 部分门结构。

公开(公告)号：US20160163604A1

公开(公告)日：2016-06-09

申请号：US14674924

申请日：2015-03-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Min Gyu Sung ,  Ryan Ryoung-Han Kim ,  Kwan-Yong Lim ,  Chanro Park

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/823878 ,  H01L21/823821 ,  H01L21/823857 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes forming first sacrificial gate structures above a fin for two active gates and a dummy gate, removing the first sacrificial gate structure for the dummy gate so as to define a cavity that exposes the fin while leaving the first sacrificial gate structures for the two active gates intact, etching through the cavity to form a trench in the fin under the cavity, forming a second sacrificial gate structure for the dummy gate, removing the first sacrificial gate structures for the two active gates and the second sacrificial gate structure for the dummy gate so as to define a replacement gate cavity for the two active gates and the dummy gate, and forming a replacement gate structure in each of the replacement gate cavities, wherein the replacement gate structure for the dummy gate extends into the trench in the fin.

Abstract translation: 本文公开的一种说明性方法包括在两个有源栅极和伪栅极的鳍片的上方形成第一牺牲栅极结构，去除用于伪栅极的第一牺牲栅极结构，以便限定在离开第一牺牲栅极结构的同时露出鳍片的空腔 对于完整的两个有源栅极，蚀刻通过空腔以在腔下方的鳍形成沟槽，形成用于伪栅极的第二牺牲栅极结构，去除用于两个有源栅极和第二牺牲栅极结构的第一牺牲栅极结构 为了形成用于两个有源栅极和虚拟栅极的替代栅极腔，并且在每个替代栅极腔中形成替代栅极结构，其中用于伪栅极的替代栅极结构延伸到沟槽中 翅膀

公开(公告)号：US09362181B1

公开(公告)日：2016-06-07

申请号：US14674924

申请日：2015-03-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Min Gyu Sung ,  Ryan Ryoung-Han Kim ,  Kwan-Yong Lim ,  Chanro Park

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L21/823878 ,  H01L21/823821 ,  H01L21/823857 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes forming first sacrificial gate structures above a fin for two active gates and a dummy gate, removing the first sacrificial gate structure for the dummy gate so as to define a cavity that exposes the fin while leaving the first sacrificial gate structures for the two active gates intact, etching through the cavity to form a trench in the fin under the cavity, forming a second sacrificial gate structure for the dummy gate, removing the first sacrificial gate structures for the two active gates and the second sacrificial gate structure for the dummy gate so as to define a replacement gate cavity for the two active gates and the dummy gate, and forming a replacement gate structure in each of the replacement gate cavities, wherein the replacement gate structure for the dummy gate extends into the trench in the fin.

Abstract translation: 本文公开的一种说明性方法包括在两个有源栅极和伪栅极的鳍片的上方形成第一牺牲栅极结构，去除用于伪栅极的第一牺牲栅极结构，以便限定在离开第一牺牲栅极结构的同时露出鳍片的空腔 对于完整的两个有源栅极，蚀刻通过空腔以在腔下方的鳍形成沟槽，形成用于伪栅极的第二牺牲栅极结构，去除用于两个有源栅极和第二牺牲栅极结构的第一牺牲栅极结构 为了形成用于两个有源栅极和虚拟栅极的替代栅极腔，并且在每个替代栅极腔中形成替代栅极结构，其中用于伪栅极的替代栅极结构延伸到沟槽中 翅膀

公开(公告)号：US09324799B2

公开(公告)日：2016-04-26

申请号：US14480974

申请日：2014-09-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Kwan-Yong Lim ,  Sukwon Hong

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/10 ,  H01L29/66 ,  H01L21/762 ,  H01L29/36 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06

CPC classification number: H01L29/7856 ,  H01L21/2253 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/36 ,  H01L29/66795 ,  H01L29/7851

Abstract: Methods of fabricating circuit structures including FinFET structures are provided, including: providing a substrate and a first material having a first threshold voltage above the substrate, and a second material having a second threshold voltage lower than the first threshold voltage above the first material; forming fins having base fin portions formed from the first material and upper fin portions formed from the second material; providing gate structures over the fins to form one or more FinFET structures, wherein the gate structures wrap around at least the upper fin portions and have an operating voltage lower than the first threshold voltage and higher than the second threshold voltage, so that the upper fin portions define a channel size of the one or more FinFET structures. Circuit structures including FinFET structures are also provided, in which the FinFET structures have a uniform channel size defined only by upper fin portions thereof.

Abstract translation: 提供了制造包括FinFET结构的电路结构的方法，包括：提供衬底和在衬底上方具有第一阈值电压的第一材料以及具有低于第一材料之上的第一阈值电压的第二阈值电压的第二材料; 形成具有由所述第一材料形成的基部翅片部分和由所述第二材料形成的上部翅片部分的翅片; 在所述翅片上提供栅极结构以形成一个或多个FinFET结构，其中所述栅极结构至少缠绕在所述上鳍部分上并具有低于所述第一阈值电压并高于所述第二阈值电压的工作电压，使得所述上翅片 部分限定一个或多个FinFET结构的通道尺寸。 还提供了包括FinFET结构的电路结构，其中FinFET结构具有仅由其上翅部分限定的均匀通道尺寸。

公开(公告)号：US09312388B2

公开(公告)日：2016-04-12

申请号：US14267216

申请日：2014-05-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Hoon Kim ,  Chanro Park ,  Min Gyu Sung

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

Abstract: One method disclosed includes, among other things, forming a gate structure above an active region of a semiconductor substrate, wherein a first portion of the gate structure is positioned above the active region and second portions of the gate structure are positioned above an isolation region formed in the substrate, forming a sidewall spacer adjacent opposite sides of the first portion of the gate structure so as to define first and second continuous epi formation trenches comprised of the spacer that extend for less than the axial length of the gate structure, and forming an epi semiconductor material on the active region within each of the first and second continuous epi formation trenches.

Abstract translation: 所公开的一种方法包括在半导体衬底的有源区上方形成栅极结构，其中栅极结构的第一部分位于有源区上方，栅极结构的第二部分位于形成的隔离区的上方 在所述衬底中，形成邻近所述栅极结构的第一部分的相对侧面的侧壁间隔物，以便限定由所述间隔物组成的第一和第二连续外延形成沟槽，所述沟槽延伸小于所述栅极结构的轴向长度，并形成 在第一和第二连续外延形成沟槽的每一个内的有源区域上的外延半导体材料。

公开(公告)号：US09312183B1

公开(公告)日：2016-04-12

申请号：US14531743

申请日：2014-11-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hoon Kim ,  Min Gyu Sung

IPC: H01L21/336 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/1083 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7854

Abstract: A method for forming FinFETs having a capping layer for reducing punch through leakage includes providing an intermediate semiconductor structure having a semiconductor substrate and a fin disposed on the semiconductor substrate. A capping layer is disposed over the fin, and an isolation fill is disposed over the capping layer. A portion of the isolation fill and the capping layer is removed to expose an upper surface portion of the fin. Tapping layer and a lower portion of the fin define an interface dipole layer barrier, a portion of the capping layer operable to provide an increased negative charge or an increased positive charge adjacent to the fin, to reduce punch-through leakage compared to a fin without the capping layer.

Abstract translation: 用于形成具有用于减少穿通漏电的封盖层的FinFET的方法包括提供具有设置在半导体衬底上的半导体衬底和鳍的中间半导体结构。 覆盖层设置在翅片上方，并且隔离填充物设置在覆盖层上。 去除隔离填充物和覆盖层的一部分以露出翅片的上表面部分。 突出层和鳍的下部限定了界面偶极层势垒，所述覆盖层的一部分可操作以提供增加的负电荷或增加与所述鳍相邻的正电荷，以减少与不具有 盖层。

公开(公告)号：US10461196B2

公开(公告)日：2019-10-29

申请号：US15662526

申请日：2017-07-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Steven Bentley ,  Ruilong Xie ,  Min Gyu Sung

IPC: H01L29/786 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: Forming a vertical FinFET includes forming a semiconductor fin on a substrate and having a fin mask on an upper surface thereof; laterally recessing the semiconductor fin causing the fin mask; forming a conformal gate liner on the recessed semiconductor fin and the fin mask, wherein the conformal gate liner includes a first portion surrounding the fin mask and a second portion surrounding the recessed fins and being separated from the fin mask by a thickness of the conformal gate liner; forming a gate mask laterally adjacent to the second portion of the conformal gate liner; removing the first portion of the conformal gate liner; removing the gate mask to expose a remaining second portion of the conformal gate liner; and forming a gate contact to the second portion of the conformal gate liner, the remaining second portion of the conformal gate liner defines the gate length.