公开(公告)号：US09379209B2

公开(公告)日：2016-06-28

申请号：US14536167

申请日：2014-11-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Jiajun Mao ,  Xusheng Wu ,  Min-hwa Chi

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/285 ,  H01L21/321 ,  H01L21/3205

CPC classification number: H01L29/66545 ,  H01L21/28079 ,  H01L21/28518 ,  H01L21/28562 ,  H01L21/32053 ,  H01L21/32115 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76867 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659

Abstract: A replacement gate structure that includes a conductive metal gate electrode is formed in a gate cavity, wherein the gate cavity is formed in a dielectric material formed above an active region of a semiconductor device. An upper surface of the conductive metal gate electrode and an upper surface of the dielectric material are planarized during a common planarization process, and a protective conductive cap is selectively formed on and in direct physical contact with the planarized upper surface of the conductive metal gate electrode. A contact structure is formed in a dielectric insulating layer formed above the replacement gate structure, the contact structure directly contacting the protective conductive cap.

Abstract translation: 包括导电金属栅电极的替代栅极结构形成在栅腔中，其中栅腔形成在形成在半导体器件的有源区上方的电介质材料中。 导电金属栅电极的上表面和电介质材料的上表面在公共平坦化工艺期间被平坦化，并且保护性导电帽选择性地形成在导电金属栅电极的平坦化上表面上并与之直接物理接触 。 接触结构形成在形成在替换栅极结构之上的电介质绝缘层中，接触结构直接接触保护性导电盖。

公开(公告)号：US20160163824A1

公开(公告)日：2016-06-09

申请号：US14560054

申请日：2014-12-04

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Dong-Woon Shin ,  Min-Hwa Chi ,  Xusheng Wu

IPC: H01L29/66 ,  H01L21/3105 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/66545 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/7848

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming sidewall spacer structures laterally adjacent to a dummy gate structure that overlies a semiconductor substrate. Additional sidewall spacer structures are formed laterally adjacent to the sidewall spacer structures and under lower portions of the sidewall spacer structures. The dummy gate structure is replaced with a replacement gate structure.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实例中，一种用于制造集成电路的方法包括在与半导体衬底上的虚拟栅极结构相邻的侧壁上形成侧壁间隔结构。 另外的侧壁间隔结构横向邻近侧壁间隔结构形成，并在侧壁间隔结构的下部形成。 虚拟栅极结构被替换为栅极结构。

公开(公告)号：US20160133721A1

公开(公告)日：2016-05-12

申请号：US14536167

申请日：2014-11-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Jiajun Mao ,  Xusheng Wu ,  Min-hwa Chi

IPC: H01L29/66 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/28 ,  H01L21/285

CPC classification number: H01L29/66545 ,  H01L21/28079 ,  H01L21/28518 ,  H01L21/28562 ,  H01L21/32053 ,  H01L21/32115 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76867 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659

Abstract: A replacement gate structure that includes a conductive metal gate electrode is formed in a gate cavity, wherein the gate cavity is formed in a dielectric material formed above an active region of a semiconductor device. An upper surface of the conductive metal gate electrode and an upper surface of the dielectric material are planarized during a common planarization process, and a protective conductive cap is selectively formed on and in direct physical contact with the planarized upper surface of the conductive metal gate electrode. A contact structure is formed in a dielectric insulating layer formed above the replacement gate structure, the contact structure directly contacting the protective conductive cap.

Abstract translation: 包括导电金属栅电极的替代栅极结构形成在栅腔中，其中栅腔形成在形成在半导体器件的有源区上方的电介质材料中。 导电金属栅电极的上表面和电介质材料的上表面在公共平坦化工艺期间被平坦化，并且保护性导电帽选择性地形成在导电金属栅电极的平坦化上表面上并与之直接物理接触 。 接触结构形成在形成在替换栅极结构之上的电介质绝缘层中，接触结构直接接触保护性导电盖。

公开(公告)号：US09275906B2

公开(公告)日：2016-03-01

申请号：US14267611

申请日：2014-05-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Xiang Hu ,  Changyong Xiao ,  Wanxun He

IPC: H01L21/8238 ,  H01L21/306 ,  H01L21/02 ,  H01L27/092 ,  H01L29/161 ,  H01L29/16 ,  H01L29/201

CPC classification number: H01L29/0657 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/0259 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0692 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/201

Abstract: A non-planar semiconductor structure includes mixed n-and-p type raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon and silicon germanium, naturally growing into a diamond shape. The surface area of the epitaxial structures is increased by removing portion(s) thereof, masking each type as the other type is grown and then subsequently modified by the removal. The removal may create multi-head (e.g., dual-head) epitaxial structures, together with the neck of the respective raised structure resembling a Y-shape.

Abstract translation: 非平面半导体结构包括混合的n型和p型凸起半导体结构，例如具有在其顶表面上生长的外延结构的散热片，例如外延硅和硅锗，天然生长成菱形。 外延结构的表面积通过去除其部分而增加，当另一种类型生长然后随后通过去除而修饰时，掩蔽每种类型。 移除可以与类似于Y形的相应凸起结构的颈部一起产生多头（例如，双头）外延结构。

公开(公告)号：US09263516B1

公开(公告)日：2016-02-16

申请号：US14823319

申请日：2015-08-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Changyong Xiao ,  Wanxun He ,  Hongliang Shen

IPC: H01L21/84 ,  H01L21/00 ,  H01L29/66 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L29/0646 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653

Abstract: An integrated circuit product is disclosed that includes a plurality of trenches in a semiconducting substrate that define first, second and third fins, wherein the fins are side-by-side, and wherein the second fin is positioned between the first and third fins, a layer of insulating material in the plurality of trenches such that a desired height of the first, second and third fins is positioned above an upper surface of the layer of insulating material, a recess defined in the second fin that at least partially defines a cavity in the layer of insulating material, an SDB isolation structure in the cavity on the recessed portion of the second fin, wherein the SDB isolation structure has an upper surface that is above the upper surface of the layer of insulating material, and a gate structure for a transistor positioned above the SDB isolation structure.

Abstract translation: 公开了一种集成电路产品，其包括限定第一，第二和第三鳍片的半导体衬底中的多个沟槽，其中散热片并排，并且其中第二鳍片位于第一和第三鳍片之间， 多个沟槽中的绝缘材料层，使得第一，第二和第三鳍片的期望高度位于绝缘材料层的上表面上方，限定在第二鳍片中的凹部，其至少部分地限定在第 所述绝缘材料层，在所述第二鳍片的凹陷部分上的空腔中的SDB隔离结构，其中所述SDB隔离结构具有位于所述绝缘材料层的上表面上方的上表面，以及用于 晶体管位于SDB隔离结构之上。

公开(公告)号：US09123773B1

公开(公告)日：2015-09-01

申请号：US14461015

申请日：2014-08-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： HongLiang Shen ,  Fangyu Wu ,  Haigou Huang ,  Xusheng Wu ,  Changyong Xiao ,  Wanxum He

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/306 ,  H01L21/308 ,  H01L21/02 ,  H01L21/3065

CPC classification number: H01L21/76224 ,  H01L21/3086 ,  H01L21/76232 ,  H01L29/66795

Abstract: Methods of forming a T-shaped SBD using a single-mask process flow are disclosed. Embodiments include providing a substrate having STI regions; forming a hard mask layer over the substrate and the STI regions, the hard mask having an opening laterally separated from the STI regions; forming a recess in the substrate through the opening, the recess having a first width; forming spacers on sidewalls of the recess, with a gap therebetween; forming a trench in the substrate through the gap, the trench having a second width less than the first; removing the spacers; removing the hard mask layer; filling the trench and the recess with an oxide layer, forming a T-shaped STI region; forming another hard mask layer on a portion of the T-shaped STI region; and revealing a Fin by removing portions of the STI regions and the T-shaped STI region.

Abstract translation: 公开了使用单掩模工艺流程形成T形SBD的方法。 实施例包括提供具有STI区域的基板; 在所述基板和所述STI区域上形成硬掩模层，所述硬掩模具有与所述STI区域横向分离的开口; 通过所述开口在所述基板中形成凹部，所述凹部具有第一宽度; 在凹槽的侧壁上形成间隔物，其间具有间隙; 通过所述间隙在所述衬底中形成沟槽，所述沟槽具有小于所述第一宽度的第二宽度; 去除垫片; 去除硬掩模层; 用氧化物层填充沟槽和凹部，形成T形STI区域; 在T形STI区域的一部分上形成另一个硬掩模层; 并且通过去除STI区域和T形STI区域的部分来显露Fin。