公开(公告)号：US11171210B2

公开(公告)日：2021-11-09

申请号：US16804435

申请日：2020-02-28

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： John J. Pekarik ,  Vibhor Jain

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/08 ,  H01L29/737

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor and methods of manufacture. The structure includes: a sub-collector region; a collector region above the sub-collector region; an intrinsic base region composed of intrinsic base material located above the collector region; an emitter located above and separated from the intrinsic base material; and a raised extrinsic base having a stepped configuration and separated from and self-aligned to the emitter.

公开(公告)号：US11171095B1

公开(公告)日：2021-11-09

申请号：US16855185

申请日：2020-04-22

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Vibhor Jain ,  Ajay Raman ,  Sebastian T. Ventrone ,  John J. Ellis-Monaghan ,  Siva P. Adusumilli ,  Yves T. Ngu

IPC: H01L23/00

Abstract: The present disclosure relates to an active x-ray attack prevention structure for secure integrated circuits. In particular, the present disclosure relates to a structure including a functional circuit, and at least one latchup sensitive diode circuit configured to induce a latchup condition in the functional circuit, placed in proximity of the functional circuit.

公开(公告)号：US20210280672A1

公开(公告)日：2021-09-09

申请号：US16807453

申请日：2020-03-03

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Vibhor Jain ,  John J. Pekarik ,  Steven M. Shank ,  John J. Ellis-Monaghan

IPC: H01L29/06 ,  H01L29/04 ,  H01L29/737 ,  H01L27/102 ,  H01L21/762

Abstract: Structures including electrical isolation and methods of forming a structure including electrical isolation. A semiconductor layer is formed over a semiconductor substrate and shallow trench isolation regions are formed in the semiconductor layer. The semiconductor layer includes single-crystal semiconductor material having an electrical resistivity that is greater than or equal to 1000 ohm-cm. The shallow trench isolation regions are arranged to surround a portion of the semiconductor layer to define an active device region. A polycrystalline layer is positioned in the semiconductor layer and extends laterally beneath the active device region and the shallow trench isolation regions that surround the active device region.

公开(公告)号：US20210183918A1

公开(公告)日：2021-06-17

申请号：US16713423

申请日：2019-12-13

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： John J. Ellis-Monaghan ,  Steven M. Shank ,  Vibhor Jain ,  Anthony K. Stamper ,  John J. Pekarik

IPC: H01L27/146

Abstract: Structures including a photodiode and methods of fabricating such structures. A trench extends from a top surface of a substrate to a depth into the substrate. The photodiode includes an active layer positioned in the trench. Trench isolation regions, which are located in the substrate, are arranged to surround the trench. A portion of the substrate is positioned in a surrounding relationship about the active layer and between the active layer and the trench isolation regions.

公开(公告)号：US20210132461A1

公开(公告)日：2021-05-06

申请号：US16674711

申请日：2019-11-05

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  Siva P. Adusumilli ,  John J. Ellis-Monaghan

IPC: G02F1/225 ,  H01L31/0232

Abstract: Structures including a photodetector and methods of fabricating such structures. A substrate, which is composed of a semiconductor material, includes a first trench, a second trench, and a pillar of the semiconductor material that is laterally positioned between the first trench and the second trench. A first portion of a dielectric layer is located in the first trench and a second portion of the dielectric layer is located in the second trench. A waveguide core is coupled to the pillar at a top surface of the substrate.

公开(公告)号：US20250120144A1

公开(公告)日：2025-04-10

申请号：US18481632

申请日：2023-10-05

Applicant: GlobalFoundries U.S. Inc.

Inventor： Uppili S. Raghunathan ,  Alexander M. Derrickson ,  Sarah A. McTaggart ,  Judson Robert Holt ,  Vibhor Jain

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/66

Abstract: The disclosure provides bipolar transistor structures with a cavity below an extrinsic base, and methods to form the same. A structure of the disclosure provides a bipolar transistor structure including an extrinsic base protruding from an intrinsic base of a bipolar transistor. The extrinsic base extends over a cavity. An insulator is horizontally adjacent the cavity and below a portion of the extrinsic base. A collector extension region of the bipolar transistor structure extends laterally below the insulator and the cavity.

公开(公告)号：US12211929B1

公开(公告)日：2025-01-28

申请号：US18663523

申请日：2024-05-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： Alexander Derrickson ,  Anupam Dutta ,  John Pekarik ,  Vibhor Jain ,  V V S S Satyasuresh Choppalli ,  Rui Tze Toh ,  Oscar Restrepo

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. The structure comprises an intrinsic base including a first semiconductor layer, a collector including a second semiconductor layer, and an emitter including a third semiconductor layer. The first semiconductor layer, which comprises silicon-germanium, includes a first portion and a second portion adjacent to the first portion. The second semiconductor layer includes a portion on the first portion of the first semiconductor layer, and the third semiconductor layer includes a portion on the second portion of the first semiconductor layer. The structure further comprises a dielectric spacer laterally between the portion of the second semiconductor layer and the portion of the third semiconductor layer.

公开(公告)号：US12204144B2

公开(公告)日：2025-01-21

申请号：US17525327

申请日：2021-11-12

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Nicholas A. Polomoff ,  Yusheng Bian ,  Vibhor Jain

IPC: G01N27/04 ,  G02B6/12 ,  G02B6/122 ,  H01L23/00

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a photonic chip security structure and methods of manufacture. The structure includes an optical component over a substrate material, and at least one vertical wall including a reflecting material within a dielectric stack of material and surrounding the optical component.

公开(公告)号：US20240170560A1

公开(公告)日：2024-05-23

申请号：US17990898

申请日：2022-11-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Alexander Derrickson ,  Venkatesh Gopinath ,  John J. Pekarik ,  Hong Yu ,  Vibhor Jain ,  David Pritchard

IPC: H01L29/735 ,  H01L27/06 ,  H01L29/66 ,  H01L29/732

CPC classification number: H01L29/735 ,  H01L27/0623 ,  H01L29/66871 ,  H01L29/732

Abstract: Structures that include bipolar junction transistors and methods of forming such structures. The structure comprises a semiconductor layer, a substrate, and a dielectric layer disposed between the semiconductor layer and the substrate. The structure further comprises a first bipolar junction transistor including a first collector in the substrate, a first emitter, and a first base layer. The first base layer extends through the dielectric layer from the first emitter to the first collector. The structure further comprises a second bipolar junction transistor including a second collector in the substrate, a second emitter, and a second base layer. The second base layer extends through the dielectric layer from the second emitter to the second collector. The second base layer is connected to the first base layer by a section of the semiconductor layer to define a base line.

公开(公告)号：US11942534B2

公开(公告)日：2024-03-26

申请号：US17745178

申请日：2022-05-16

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hong Yu ,  Judson R. Holt ,  Vibhor Jain

IPC: H01L29/737 ,  H01L23/373 ,  H01L29/66

CPC classification number: H01L29/737 ,  H01L23/3738 ,  H01L29/66242

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with thermal conductor and methods of manufacture. The structure includes: a base formed within a semiconductor substrate; a thermal conductive material under the base and extending to an underlying semiconductor material; an emitter on a first side of the base; and a collector on a second side of the base.