公开(公告)号：US10153361B2

公开(公告)日：2018-12-11

申请号：US15360295

申请日：2016-11-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Renata A. Camillo-Castillo ,  Vibhor Jain ,  Qizhi Liu ,  Anthony K. Stamper

IPC: H01L29/737 ,  H01L21/8222 ,  H01L21/02 ,  H01L21/268 ,  H01L21/324 ,  H01L27/082 ,  H01L29/04 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66 ,  H03F3/21

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to heterojunction bipolar transistor device integration schemes on a same wafer and methods of manufacture. The structure includes: a power amplifier (PA) device comprising a base, a collector and an emitter on a wafer; and a low-noise amplifier (LNA) device comprising a base, a collector and an emitter on the wafer, with the emitter having a same crystalline structure as the base.

公开(公告)号：US20180012845A1

公开(公告)日：2018-01-11

申请号：US15713756

申请日：2017-09-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Mukta G. Farooq ,  John A. Fitzsimmons

IPC: H01L23/532 ,  H01L23/00 ,  H01L21/762 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L23/53238 ,  H01L21/76251 ,  H01L21/76254 ,  H01L23/481 ,  H01L23/522 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05147

Abstract: An SOI semiconductor device includes a first wafer having an active semiconductor layer and a first oxide layer and a second wafer having a semiconductor substrate and a second oxide layer, the first oxide layer being bonded to the second oxide layer, and one of the first wafer and the second wafer includes a nitride layer. The nitride layer can be formed between the semiconductor substrate and the second oxide layer. A third oxide layer can be formed on the semiconductor substrate and the nitride layer is formed between the second oxide layer and the third oxide layer. The nitride layer can be formed between the active semiconductor layer and the first oxide layer. The first wafer can include a third oxide layer formed on the active semiconductor layer and the nitride layer is formed between the third oxide layer and the first oxide layer.

公开(公告)号：US09728603B2

公开(公告)日：2017-08-08

申请号：US14745764

申请日：2015-06-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hanyi Ding ,  Vibhor Jain ,  Alvin J. Joseph ,  Anthony K. Stamper

IPC: H01L29/00 ,  H01L29/08 ,  H01L29/73 ,  H01L29/66 ,  H01L29/737 ,  H01L29/06

CPC classification number: H01L29/0813 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/73 ,  H01L29/7371 ,  H01L29/7378

Abstract: Device structures for a bipolar junction transistor and methods of fabricating a device structure for a bipolar junction transistor. A base layer comprised of a first semiconductor material is formed. An emitter layer comprised of a second semiconductor material is formed on the base layer. The emitter layer is patterned to form an emitter finger having a length and a width that changes along the length of the emitter finger.

公开(公告)号：US09673220B1

公开(公告)日：2017-06-06

申请号：US15065331

申请日：2016-03-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Randy L. Wolf ,  Mark D. Jaffe

IPC: H01L27/12 ,  H01L29/06 ,  H01L23/528 ,  H01L23/522 ,  H01L29/423 ,  H01L29/417 ,  H01L29/08 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/683 ,  H01L21/768

CPC classification number: H01L27/1203 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823475 ,  H01L21/84 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/124 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/4175 ,  H01L29/4238 ,  H01L29/42384 ,  H01L29/78618

Abstract: Chip structures that include distributed wiring layouts and fabrication methods for forming such chip structures. A device structure is formed that includes a plurality of first device regions and a plurality of second device regions. A first wiring level is formed that includes a first wire coupled with the first device regions. A second wiring level is formed that includes a second wire coupled with the second device regions. The first wiring level is vertically separated from the second wiring level by a buried oxide layer of the silicon-on-insulator substrate.

公开(公告)号：US20160372582A1

公开(公告)日：2016-12-22

申请号：US14745704

申请日：2015-06-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Renata Camillo-Castillo ,  Hanyi Ding ,  Natalie B. Feilchenfeld ,  Vibhor Jain ,  Anthony K. Stamper

IPC: H01L29/73 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L29/732

CPC classification number: H01L29/0821 ,  H01L21/762 ,  H01L21/76283 ,  H01L29/0653 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7371

Abstract: Methods for forming a device structure and device structures using a silicon-on-insulator substrate that includes a high-resistance handle wafer. A doped region is formed in the high-resistance handle wafer. A first trench is formed that extends through a device layer and a buried insulator layer of the silicon-on-insulator substrate to the high-resistance handle wafer. The doped region includes lateral extension of the doped region extending laterally of the first trench. A semiconductor layer is epitaxially grown within the first trench, and a device structure is formed using at least a portion of the semiconductor layer. A second trench is formed that extends through the device layer and the buried insulator layer to the lateral extension of the doped region, and a conductive plug is formed in the second trench. The doped region and the plug comprise a body contact.

Abstract translation: 使用包括高电阻处理晶片的绝缘体上硅衬底形成器件结构和器件结构的方法。 在高电阻处理晶片中形成掺杂区域。 形成第一沟槽，其延伸穿过绝缘体上硅衬底的器件层和掩埋绝缘体层到高电阻处理晶片。 掺杂区域包括在第一沟槽横向延伸的掺杂区域的横向延伸。 半导体层在第一沟槽内外延生长，并且使用半导体层的至少一部分形成器件结构。 形成第二沟槽，其延伸穿过器件层和掩埋绝缘体层到掺杂区域的横向延伸，并且在第二沟槽中形成导电插塞。 掺杂区域和插塞包括身体接触。

公开(公告)号：US09425269B1

公开(公告)日：2016-08-23

申请号：US14747604

申请日：2015-06-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Anthony K. Stamper

IPC: H01L21/768 ,  H01L29/417 ,  H01L29/40

CPC classification number: H01L29/41708 ,  H01L21/76804 ,  H01L21/76829 ,  H01L29/401 ,  H01L29/73

Abstract: Device structures for a bipolar junction transistor and methods for fabricating such device structures. An emitter structure is formed that has a semiconductor layer with a top surface defining a recess and a sacrificial layer comprised of a disposable material in the recess. A contact opening is formed that extends through one or more first dielectric layers to the sacrificial layer. After the contact opening is formed, the sacrificial layer is removed from the recess. Alternatively, the layer in the recess may be comprised of a non-disposable material that may occupy the recess at the time that a contact is formed in the contact opening.

Abstract translation: 双极结型晶体管的器件结构及其制造方法。 形成发射体结构，其具有半导体层，其具有限定凹部的顶表面和在凹部中由一次性材料构成的牺牲层。 形成了延伸穿过一个或多个第一介电层到牺牲层的接触开口。 在形成接触开口之后，从凹部移除牺牲层。 或者，凹部中的层可以由在接触开口中形成接触时可能占据凹部的非一次性材料构成。

公开(公告)号：US09299765B2

公开(公告)日：2016-03-29

申请号：US14687049

申请日：2015-04-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel C. Edelstein ,  Anthony K. Stamper

IPC: H01G5/00 ,  H01L49/02 ,  H01G7/02 ,  H01G7/04 ,  H01G7/06

CPC classification number: H01L28/75 ,  H01G7/026 ,  H01G7/04 ,  H01G7/06 ,  H01L28/40 ,  Y10T29/417

Abstract: Embodiments include a metal-insulator-metal (MIM) capacitor having: a first electrode; a second electrode disposed proximate the first electrode; an insulator layer between the first and second electrodes; and a reactive layer positioned proximate the insulator layer and configured to allow altering of the reactive layer to change a capacitive value of the MIM capacitor, the reactive layer including a reactive conductor.

Abstract translation: 实施例包括具有：第一电极的金属 - 绝缘体 - 金属（MIM）电容器; 设置在所述第一电极附近的第二电极; 第一和第二电极之间的绝缘体层; 以及反应层，其位于绝缘体层附近并被配置为允许改变反应层以改变MIM电容器的电容值，反应层包括反应性导体。