-
公开(公告)号：US06790790B1
公开(公告)日：2004-09-14
申请号：US10302227
申请日：2002-11-22
IPC分类号： H01L2131
CPC分类号： H01L21/31058 , H01L21/02118 , H01L21/0212
摘要： Disclosed are methods for processing a low k material involving providing a low k material layer comprising one or more low k polymer materials and one or more high modulus fillers on a semiconductor substrate, and chemical mechanical polishing the low k material layer so as to remove a portion of the low k material layer from the semiconductor substrate without substantially damaging unremoved portions of the low k material layer. In this connection, low k material layers for a semiconductor structure containing one or more low k polymer materials and one or more high modulus fillers are disclosed, as well as methods of making the low k material layers.
摘要翻译： 公开了一种处理低k材料的方法，包括在半导体衬底上提供包含一种或多种低k聚合物材料和一种或多种高模量填料的低k材料层，以及化学机械抛光低k材料层，以除去 来自半导体衬底的低k材料层的一部分，而不会基本上损坏低k材料层的未被除去的部分。 在这方面，公开了用于包含一种或多种低k聚合物材料和一种或多种高模量填料的半导体结构的低k材料层，以及制备低k材料层的方法。
-
102.发明授权Sensor to predict void free films using various grating structures and characterize fill performance 失效传感器预测使用各种光栅结构的无空隙膜，并表征填充性能公开(公告)号：US06684172B1
公开(公告)日：2004-01-27
申请号：US10034165
申请日：2001-12-27
申请人： Ramkumar Subramanian , Steven C. Avanzino , Christopher F. Lyons , Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh , Cyrus E. Tabery
发明人： Ramkumar Subramanian , Steven C. Avanzino , Christopher F. Lyons , Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh , Cyrus E. Tabery
IPC分类号： G01L2500
CPC分类号： C23C16/52 , C23C14/547 , C23C18/1675 , C25D21/12 , H01L21/76877
摘要： One aspect of the invention relates to a metal fill process and systems therefor involving providing a standard calibration wafer having a plurality of fill features of known dimensions in a metalization tool; depositing a metal material over the standard calibration wafer; monitoring the deposition of metal material using a sensor system, the sensor system operable to measure one or more fill process parameters and to generate fill process data; controlling the deposition of metal material to minimize void formation using a control system wherein the control system receives fill process data from the sensor system and analyzes the fill process data to generate a feed-forward control data operative to control the metalization tool; and depositing metal material over a production wafer in the metalization tool using the fill process data generated by the sensor system and the control system. The invention further relates to tool characterization processes and systems therefor.
摘要翻译： 本发明的一个方面涉及一种金属填充方法及其系统，其涉及在金属化工具中提供具有已知尺寸的多个填充特征的标准校准晶片; 在标准校准晶片上沉积金属材料; 使用传感器系统监测金属材料的沉积，所述传感器系统可操作以测量一个或多个填充过程参数并产生填充过程数据; 控制金属材料的沉积以最小化使用控制系统的空隙形成，其中控制系统从传感器系统接收填充过程数据并分析填充过程数据以产生可操作以控制金属化工具的前馈控制数据; 以及使用由传感器系统和控制系统产生的填充过程数据在金属化工具中的生产晶片上沉积金属材料。 本发明还涉及其工具表征过程及其系统。
-
103.发明授权公开(公告)号：US06605413B1
公开(公告)日：2003-08-12
申请号：US10230171
申请日：2002-08-29
IPC分类号： G03F726
CPC分类号： G03F7/40 , G03F7/2024 , G03F7/405
摘要： There is provided a method for forming a photoresist layer for photolithographic applications which has increased structural strength. The photoresist layer is exposed through a mask and developed. The photoresist layer is then reacted with a stabilizer agent to change its material properties before the photoresist layer is dried. Also provided are a semiconductor fabrication method employing a stabilizer-treated photoresist and a composition for a photoresist that strengthens when exposed to a stabilizer agent.
摘要翻译： 提供了一种用于形成光刻应用的光致抗蚀剂层的方法，其具有增加的结构强度。 光致抗蚀剂层通过掩模曝光并显影。 然后光致抗蚀剂层与稳定剂反应以在光致抗蚀剂层干燥之前改变其材料性质。 还提供了使用稳定剂处理的光致抗蚀剂的半导体制造方法和当暴露于稳定剂时增强的光致抗蚀剂组合物。
-
公开(公告)号：US06423650B1
公开(公告)日：2002-07-23
申请号：US09371715
申请日：1999-08-09
IPC分类号： H01L2131
摘要： In one embodiment, the present invention relates to a method of processing a semiconductor substrate, involving the steps of providing the semiconductor substrate having an upper surface; roughening the upper surface of the semiconductor substrate so that the upper surface of the semiconductor substrate has an Rtm of about 10 Å or more; and depositing an ultra-thin photoresist on the upper surface of the semiconductor substrate, the ultra-thin photoresist having a thickness of about 2,000 Å or less.
-
公开(公告)号：US06391525B1
公开(公告)日：2002-05-21
申请号：US09482256
申请日：2000-01-13
申请人： Christopher F. Lyons
发明人： Christopher F. Lyons
IPC分类号： G03F700
CPC分类号： G03F7/00 , G03F7/0035 , G03F7/0045 , H01L21/0337 , H01L21/0338 , H01L21/28132 , H01L21/3088 , H01L21/32136 , H01L21/32137 , H01L21/32139 , H01L21/76838 , H01L21/76885
摘要： In one embodiment, the present invention relates to a method of forming a circuit structure containing at least one sub-lithographic gate conductor involving the steps of providing a substrate comprising active regions and a preliminary gate conductor film over portions of the substrate and portions of the active regions; forming a sidewall template mask having at least one sidewall over a portion of the preliminary gate conductor film that is positioned over portions of the active regions; forming a sidewall film over the sidewall template mask, the sidewall film having a vertical portion adjacent the sidewall of the sidewall template mask and a horizontal portion in areas not adjacent the sidewall of the sidewall template mask; removing the horizontal portion of the sidewall film exposing a portion of the sidewall template mask and removing the sidewall template mask; providing a second mask over the portions of the preliminary gate conductor film that are not positioned over portions of the active regions; removing exposed portions of the preliminary gate conductor film thereby forming the circuit structure containing the sub-lithographic gate conductor and gate conductors; providing a trim mask over the active regions, portions of the sub-lithographic gate conductor and the gate conductors; and removing exposed portions of the sidewall film and portions of the preliminary gate conductor film under the sidewall film.
摘要翻译： 在一个实施例中，本发明涉及一种形成包含至少一个子光刻栅极导体的电路结构的方法，该方法包括以下步骤：在衬底的部分上提供包括有源区和初步栅导体膜的衬底， 活跃地区; 形成侧壁模板掩模，所述侧壁模板掩模具有位于所述有源区的部分上方的所述预选导体膜的一部分上的至少一个侧壁; 在所述侧壁模板掩模上形成侧壁膜，所述侧壁膜具有邻近所述侧壁模板掩模的侧壁的垂直部分和不邻近所述侧壁模板掩模的侧壁的区域中的水平部分; 去除暴露所述侧壁模板掩模的一部分并去除所述侧壁模板掩模的所述侧壁膜的水平部分; 在预置栅极导体膜的未位于有源区的部分上的部分上提供第二掩模; 去除预置栅极导体膜的暴露部分，从而形成包含副光刻栅极导体和栅极导体的电路结构; 在有源区域上提供修整掩模，在次光栅栅极导体和栅极导体的部分上; 并且除去侧壁膜的暴露部分和预侧栅导体膜的侧壁膜下面的部分。
-
106.发明授权公开(公告)号：US06291137B1
公开(公告)日：2001-09-18
申请号：US09234380
申请日：1999-01-20
IPC分类号： G03C500
CPC分类号： H01L21/76885 , H01L21/28132 , H01L21/32136 , H01L21/32137 , H01L21/32139
摘要： In one embodiment, the present invention relates to a method of forming a conductive structure having a width of about 100 nm or less, involving the steps of providing a substrate having a conductive film; patterning a sidewall template over a first portion of the conductive film wherein a second portion of the conductive film is exposed, the sidewall template having at least one sidewall over the conductive film; depositing a sidewall film over the conductive film and the sidewall template, the sidewall film having a vertical portion adjacent the sidewall of the sidewall template and a horizontal portion in areas not adjacent the sidewall of the sidewall template; removing the horizontal portion of the sidewall film exposing a third portion of the conductive film; removing the sidewall template exposing a fourth portion of the conductive film; and etching the third portion and the fourth portion of the conductive film thereby providing the conductive structure having a width of about 100 nm or less underlying the vertical portion of the sidewall film.
摘要翻译： 在一个实施例中，本发明涉及一种形成宽度为约100nm或更小的导电结构的方法，包括提供具有导电膜的基板的步骤; 在所述导电膜的第一部分上图案化侧壁模板，其中所述导电膜的第二部分被暴露，所述侧壁模板在所述导电膜上具有至少一个侧壁; 在所述导电膜和所述侧壁模板上沉积侧壁膜，所述侧壁膜具有邻近所述侧壁模板的侧壁的垂直部分和在不邻近所述侧壁模板的侧壁的区域中的水平部分; 去除暴露导电膜的第三部分的侧壁膜的水平部分; 去除暴露导电膜的第四部分的侧壁模板; 并且蚀刻导电膜的第三部分和第四部分，从而提供具有约100nm或更小的宽度在该侧壁膜的垂直部分下方的导电结构。
-
107.发明授权公开(公告)号：US06245493B1
公开(公告)日：2001-06-12
申请号：US09205738
申请日：1998-12-04
申请人： Bhanwar Singh , Bharath Rangarajan , Sanjay K. Yedur , Michael K. Templeton , Christopher F. Lyons
发明人： Bhanwar Singh , Bharath Rangarajan , Sanjay K. Yedur , Michael K. Templeton , Christopher F. Lyons
IPC分类号： G03F700
CPC分类号： H01L21/0276 , G03F7/091 , G03F7/16 , H01L21/3105
摘要： A method for creating a roughened surface on a material exposed to light during a photolithographic process is provided. The roughened surface is created on a surface of the material via a plasma etch process. The roughened surface diffuses light incident to the material such that the diffused light causes insubstantial damage to a photoresist subsequently formed on the material.
摘要翻译： 提供了一种在光刻过程中在暴露于光的材料上产生粗糙表面的方法。 通过等离子体蚀刻工艺在材料的表面上形成粗糙表面。 粗糙表面扩散入射到材料的光，使得漫射的光对随后在材料上形成的光致抗蚀剂造成非实质的损坏。
-
108.发明授权公开(公告)号：US06239031B1
公开(公告)日：2001-05-29
申请号：US09487493
申请日：2000-01-19
申请人： Nick Kepler , Olov Karlsson , Larry Wang , Basab Bandyopadhyah , Effiong Ibok , Christopher F. Lyons
发明人： Nick Kepler , Olov Karlsson , Larry Wang , Basab Bandyopadhyah , Effiong Ibok , Christopher F. Lyons
IPC分类号： H01L21302
CPC分类号： G03F9/7076 , G03F9/70 , H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： Accurate photolighographic processing is achieved employing a stepper global alignment structure enabling formation thereon of a substantially transparent layer having a substantially planar upper surface. Embodiments include a set of global alignment marks comprising spaced apart trenches, each trench segmented into a plurality of narrow trenches spaced apart by uprights and forming a dummy topographical area of narrow trenches surrounding the set of alignment marks. The segmented trenches and the dummy topographical area effectively provide a substantially uniform topography enabling deposition of a transparent layer without steps and effective local planarization. Since the upper surface of the transparent layer is substantially planar, layers of material deposited on the transparent layer during subsequent processing also have a substantially planar upper surface, thereby enabling transmission of the signal produced by the alignment marks to the stepper with minimal distortion.
摘要翻译： 使用步进全局对准结构可实现准确的视差处理，该结构能够在其上形成具有基本平坦的上表面的基本透明的层。 实施例包括一组包括间隔开的沟槽的全局对准标记，每个沟槽被分段成由立柱间隔开的多个窄沟槽，并形成围绕该组对准标记的窄沟槽的虚拟地形区域。 分段沟槽和虚拟地形区域有效地提供基本均匀的形貌，使得能够沉积透明层而无需步骤和有效的局部平面化。 由于透明层的上表面基本上是平面的，因此在随后的处理期间沉积在透明层上的材料层也具有基本平坦的上表面，从而能够以最小的变形将由对准标记产生的信号传输到步进机。
-
109.发明授权Resist developing method and apparatus with nozzle offset for uniform developer application 有权用于均匀显影剂应用的具有喷嘴偏移的显影方法和装置公开(公告)号：US06210050B1
公开(公告)日：2001-04-03
申请号：US09203297
申请日：1998-12-01
IPC分类号： G03D500
CPC分类号： G03F7/3021 , G03D5/04
摘要： A resist developing method and apparatus for developing resist formed on a semiconductor wafer includes a rotating platform for supporting the wafer and a nozzle for applying developer to the resist. The nozzle is situated above the wafer and is positioned to be offset from an axis of rotation of the wafer during application of the developer to the resist. During application of the developer, the wafer is rotated at a rotational speed which allows the developer to remain on the wafer without flowing past the semiconductor edges. The developer is preferably applied for a time period less than or equal to 2 seconds.
摘要翻译： 用于在半导体晶片上形成的用于显影抗蚀剂的抗蚀剂显影方法和装置包括用于支撑晶片的旋转平台和用于将显影剂施加到抗蚀剂的喷嘴。 喷嘴位于晶片上方并且被定位成在将显影剂施加到抗蚀剂期间偏离晶片的旋转轴线。 在施加显影剂期间，晶片以允许显影剂保持在晶片上而不流过半导体边缘的转速旋转。 显影剂优选地施加小于或等于2秒的时间。
-
公开(公告)号：US06156480A
公开(公告)日：2000-12-05
申请号：US336455
申请日：1999-06-18
申请人： Christopher F. Lyons
发明人： Christopher F. Lyons
摘要： In one embodiment, the present invention relates to a method of forming a short wavelength thin photoresist coating having a low defect density by depositing sequentially at least two discrete ultra-thin photoresist layers to form the short wavelength thin photoresist coating, each ultra-thin photoresist layer independently having a thickness from about from about 200 .ANG. to about 2,500 .ANG., the short wavelength thin photoresist coating, having a thickness of about 5,000 .ANG. or less.
摘要翻译： 在一个实施方案中，本发明涉及通过依次沉积至少两个分立的超薄光致抗蚀剂层形成短波长薄光致抗蚀剂涂层，形成具有低缺陷密度的短波长薄光刻胶涂层的方法，每个超薄光致抗蚀剂 层，其厚度约为约200至约2500，短波长薄的光致抗蚀剂涂层具有约5,000或更小的厚度。
-
-
-
-
-
-
-
-
-
搜索结果
145 条记录 (耗时 0.051 秒)
