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796 条记录 (耗时 0.046 秒)

    Semiconductor device
    101.
    发明申请
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US20050181680A1

    公开(公告)日：2005-08-18

    申请号：US11050708

    申请日：2005-02-07

    申请人： Hiroyuki Takahashi ,  Masayuki Yanagisawa ,  Masatoshi Sonoda ,  Yoshinori Ueno

    发明人： Hiroyuki Takahashi ,  Masayuki Yanagisawa ,  Masatoshi Sonoda ,  Yoshinori Ueno

    IPC分类号： H01L21/82 ,  H01L21/768 ,  H01L23/525 ,  H01R12/00

    CPC分类号： H01L23/5258 ,  H01L21/268 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device wherein return wires corresponding to a plurality of fuse wires are arranged collectively in the same region. Moreover, the return wires are arranged in multiple layers. This arrangement creates a region where no return wire is disposed between the fuse wires, thereby permitting an arrangement of the fuse wires at the minimum wiring pitch. Alternatively, the semiconductor device may include fuse strings arranged in a plurality of stages and a plurality of connection wires for supplying signals to the fuse strings in the plurality of stages, respectively, wherein connection wires for other fuse strings are arranged in a region between adjacent fuse strings.

    摘要翻译： 一种半导体器件，其中对应于多个熔丝的返回线集中地布置在相同的区域中。 此外，返回线布置成多层。 这种布置形成了在熔丝之间不设置返回布线的区域，从而允许以最小布线间距布置熔丝。 或者，半导体器件可以包括分别布置在多个级中的熔丝串和用于分别向多个级中的熔丝串提供信号的多个连接线，其中用于其它熔丝串的连接线布置在相邻 保险丝串。

    Method of bending pipe and apparatus therefor
    102.
    发明申请
    Method of bending pipe and apparatus therefor 失效
    弯管及其设备的方法

    公开(公告)号：US20050172692A1

    公开(公告)日：2005-08-11

    申请号：US11016451

    申请日：2004-12-17

    申请人： Hiroyuki Takahashi ,  Hiroshi Takada

    发明人： Hiroyuki Takahashi ,  Hiroshi Takada

    IPC分类号： B21D7/06 ,  B21C37/28 ,  B21D9/07 ,  B21D9/08

    CPC分类号： B21C37/286 ,  B21D9/08

    摘要： A movable die base (2) is moved toward a stationary die base (1). A pressing force is applied by a bending punch (21) disposed on the movable die base to a bending target portion of a pipe (A) which is placed on a die (11) provided on the stationary die base and which has inserted therein a core metal (17). At the time of this bending work, both ends of the pipe are restricted by holding them with restriction pads (22). When the pressing force is applied by the bending punch, the restriction pads are displaced to follow the pressing of the bending punch, whereby restricted state on both ends of the pipe is constantly maintained.

    摘要翻译： 可动模座（2）朝静止模座（1）移动。 通过设置在可动模座上的弯曲冲头（21）将压力施加到管（A）的弯曲目标部分，管（A）放置在设置在固定模座上的模具（11）上并插入其中 芯金属（17）。 在该弯曲加工时，通过用限制垫（22）保持管的两端受到限制。 当通过弯曲冲头施加按压力时，限制垫被移动以跟随弯曲冲头的按压，从而不断地保持管道两端的受限状态。

    Semiconductor memory and method for entering its operation mode
    103.
    发明授权
    Semiconductor memory and method for entering its operation mode 失效
    半导体存储器和进入其操作模式的方法

    公开(公告)号：US06925016B2

    公开(公告)日：2005-08-02

    申请号：US10467031

    申请日：2002-01-30

    申请人： Hiroyuki Takahashi ,  Takato Shimoyama ,  Takashi Kusakari

    发明人： Hiroyuki Takahashi ,  Takato Shimoyama ,  Takashi Kusakari

    IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/403 ,  G11C11/406 ,  G11C7/00

    CPC分类号： G11C7/1045

    摘要： There is provided a method of entry of an operation mode of a semiconductor memory during operations without need of any specific timing specification and with effective suppression to any erroneous entry. If read cycles for plural addresses are continued, then, a request for entry of operation mode is accepted. In write cycles following to those read cycles, an operation mode to be entered is decided based on data externally designated, wherein in the first write cycle, the kind of the operation mode is set, and then in the next write cycle, conditions for the operation mode are set for the entry of the operation mode of the semiconductor memory.

    摘要翻译： 提供了一种在操作期间输入半导体存储器的操作模式的方法，而不需要任何特定的时序指定并有效抑制任何错误的输入。 如果持续多个地址的读取周期，则接受进入操作模式的请求。 在这些读取周期之后的写入周期中，基于外部指定的数据来决定要输入的操作模式，其中在第一写入周期中，设置操作模式的种类，然后在下一个写入周期中， 操作模式被设置用于输入半导体存储器的操作模式。

    Display device having driving circuit
    105.
    发明授权
    Display device having driving circuit 有权
    具有驱动电路的显示装置

    公开(公告)号：US06903717B2

    公开(公告)日：2005-06-07

    申请号：US10243210

    申请日：2002-09-13

    申请人： Hiroyuki Takahashi ,  Katsuhiko Yarita

    发明人： Hiroyuki Takahashi ,  Katsuhiko Yarita

    IPC分类号： G02F1/1345 ,  G09F9/00 ,  G09F9/30 ,  G09G3/20 ,  G09G3/36 ,  G09G5/00

    CPC分类号： G02F1/1345 ,  G02F2001/13456 ,  G09G3/3648

    摘要： A display device of the present invention has a drain driver mounted to a display substrate and having a gate driver and a controller therein, and also has a power source mounted to a flexible printed board and supplying a power voltage to the gate driver. The wiring of a common control signal outputted from the controller and commonly used in control of the gate driver and the power source is formed on the display substrate so that the number of pads for connecting the display substrate and the flexible printed board is reduced. Thus, the construction of the flexible printed board is simplified, and the entire display device can be made compact.

    摘要翻译： 本发明的显示装置具有安装在显示基板上并具有栅极驱动器和控制器的漏极驱动器，并且还具有安装到柔性印刷电路板的电源并向栅极驱动器提供电源电压。 在显示基板上形成从控制器输出的通用控制信号的布线，并且通常用于栅极驱动器和电源的控制，使得用于连接显示基板和柔性印刷电路板的焊盘的数量减少。 因此，简化了柔性印刷电路板的结构，并且可以使整个显示装置紧凑。

    Semiconductor memory, method for controlling refreshment of it, and method for setting memory cell array specific area for realizing the control method
    106.
    发明授权
    Semiconductor memory, method for controlling refreshment of it, and method for setting memory cell array specific area for realizing the control method 有权
    半导体存储器，其控制刷新的方法以及用于设定用于实现该控制方法的存储单元阵列特定区域的方法

    公开(公告)号：US06898142B2

    公开(公告)日：2005-05-24

    申请号：US10415604

    申请日：2001-10-23

    申请人： Hiroyuki Takahashi

    发明人： Hiroyuki Takahashi

    IPC分类号： G11C11/401 ,  G11C11/403 ,  G11C11/406 ,  G11C7/00

    CPC分类号： G11C11/40618 ,  G11C11/406 ,  G11C11/40622 ,  G11C2211/4061 ,  G11C2211/4067

    摘要： In accordance with the present invention, in order to reduce an averaged consumption current in a stand-by state, there is provided a semiconductor memory device including a memory cell array area which is divided into a plurality of areas, wherein the semiconductor memory device includes: at least one specific area setting unit being electrically coupled to said memory cell array area and adopted to set at least one area defined in said plurality of areas in accordance with an optional criterion; and at least one refresh operation control unit being electrically coupled to said memory cell array area and adopted to perform a refresh operation to the specific area based on at least one kind of specific refresh control signal, which is longer in cycle than a basic refresh control signal at least in a predetermined state of the semiconductor memory device.

    摘要翻译： 根据本发明，为了降低待机状态下的平均消耗电流，提供了一种半导体存储器件，其包括被划分为多个区域的存储单元阵列区域，其中半导体存储器件包括 至少一个特定区域设定单元电耦合到所述存储单元阵列区域，并被采用以根据可选标准设置在所述多个区域中定义的至少一个区域; 以及至少一个刷新操作控制单元，其电耦合到所述存储单元阵列区域，并且被采用以基于与基本刷新控制相比周期长的至少一种特定刷新控制信号来对所述特定区域执行刷新操作 信号至少在半导体存储器件的预定状态。

    Semiconductor memory device and control method thereof
    107.
    发明申请
    Semiconductor memory device and control method thereof 有权
    半导体存储器件及其控制方法

    公开(公告)号：US20050105380A1

    公开(公告)日：2005-05-19

    申请号：US10985876

    申请日：2004-11-12

    申请人： Hiroyuki Takahashi ,  Takato Shimoyama ,  Takuya Hirota

    发明人： Hiroyuki Takahashi ,  Takato Shimoyama ,  Takuya Hirota

    IPC分类号： G11C11/407 ,  G11C5/06 ,  G11C8/00

    CPC分类号： G11C5/066

    摘要： A semiconductor memory device has common terminals shared between a part or all of address terminals for receiving n bits of an address signal and data terminals for outputting a data signal with its bit width of n bits or less and dedicated address terminals for receiving m bits of the address signal, wherein at the time of a read, after the n bits of the address signal have been input, a plurality of data signals within a selected page are consecutively read out through the common terminals using the m bits of the address signal input from the dedicated address terminals.

    摘要翻译： 半导体存储器件具有用于接收地址信号的n位的一部分或所有地址端之间的公共端子，以及用于输出其位宽为n位或更少的数据信号的数据端，以及用于接收m位的专用地址端 地址信号，其中在读取时，在输入了地址信号的n位之后，通过地址信号输入的m位，通过公共端连续地读出选定页内的多个数据信号 从专用地址终端。

    Semiconductor storage device having a plurality of operation modes
    109.
    发明授权
    Semiconductor storage device having a plurality of operation modes 失效
    具有多种操作模式的半导体存储装置

    公开(公告)号：US06879537B2

    公开(公告)日：2005-04-12

    申请号：US10492765

    申请日：2002-10-16

    申请人： Hiroyuki Takahashi ,  Atsushi Nakagawa

    发明人： Hiroyuki Takahashi ,  Atsushi Nakagawa

    IPC分类号： G11C11/403 ,  G11C7/20 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/408 ,  G11C7/00

    CPC分类号： G11C11/40615 ,  G11C7/20 ,  G11C11/406 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2207/2227 ,  G11C2211/4067 ,  G11C2211/4068

    摘要： An operation control circuit is provided for shortening a transition time from a deep stand-by mode to a stand-by mode in a pseudo-SRAM having the deep stand-by mode and the stand-by mode. The transition from the deep stand-by mode to the stand-by mode starts first and second timer circuits which respectively output a timer output TN of a constant cycle needed for self-refresh and a timing signal TR of a shorter cycle than a self-refresh cycle. A counter circuit counts the output TR from the second timer circuit immediately after the deep stand-by mode has been transitioned to the stand-by mode. If the counted value corresponds to a value as set, then the counter circuit outputs an operation mode switching signal. A selector circuit comprising a multiplexer is switched and controlled by the output from the counter circuit. The selector circuit remains selecting TR until the counted value of the counter circuit corresponds to the set value, and in the subsequent stand-by mode, the selector circuit selects and outputs TN.

    摘要翻译： 提供一种操作控制电路，用于在具有深度待机模式和待机模式的伪SRAM中缩短从深度备用模式到待机模式的转换时间。 从深度待机模式到待机模式的转变开始分别输出自刷新所需的恒定周期的定时器输出TN和比自动刷新短的周期的定时信号TR的第一和第二定时器电路， 刷新周期。 在深度待机模式已经转换到待机模式之后，计数器电路立即对来自第二定时器电路的输出TR进行计数。 如果计数值对应于设定的值，则计数器电路输出操作模式切换信号。 包括多路复用器的选择器电路由计数器电路的输出转换和控制。 选择器电路保持选择TR，直到计数器电路的计数值对应于设定值，并且在随后的待机模式中，选择器电路选择和输出TN。