公开(公告)号：US5852380A

公开(公告)日：1998-12-22

申请号：US731437

申请日：1996-10-15

申请人： Hiroyuki Yamauchi

发明人： Hiroyuki Yamauchi

IPC分类号： G06F1/10 ,  H03K5/13 ,  H03K5/15 ,  H03L7/081 ,  H03K5/26

CPC分类号： H03K5/1508 ,  G06F1/10 ,  H03K5/133 ,  H03L7/0814

摘要： A phase adjusting circuit includes a circuit for providing an internal clock signal in synchronization with a reference clock signal, a delay circuit for delaying the internal clock signal for a predetermined delay time and an adjusting section for adjusting a phase difference between a phase of the reference clock signal and a phase of the internal clock signal delayed for the predetermined delay time.

摘要翻译： 相位调整电路包括用于与基准时钟信号同步地提供内部时钟信号的电路，用于将内部时钟信号延迟预定延迟时间的延迟电路和用于调整参考时钟相位之间的相位差的调整部分 时钟信号和内部时钟信号的相位延迟了预定的延迟时间。

公开(公告)号：US5835952A

公开(公告)日：1998-11-10

申请号：US808938

申请日：1997-02-28

申请人： Hiroyuki Yamauchi ,  Kazuhiro Matsuyama

发明人： Hiroyuki Yamauchi ,  Kazuhiro Matsuyama

IPC分类号： G06F12/06 ,  G09G5/39 ,  G09G5/399 ,  G11C7/10 ,  G11C7/12 ,  G11C7/22 ,  G11C11/00

CPC分类号： G11C11/005 ,  G06F12/0607 ,  G09G5/399 ,  G11C7/1042 ,  G11C7/12 ,  G11C7/22

摘要： An image data memory with a 2-bank (bank A and bank B) structure is disclosed. The bank A stores only even field data, whereas the bank B stores only odd field data, and a peripheral circuit composed of elements such as row decoders and column decoders is provided in such a manner that each bank can be accessed independently of the other. One of the banks A and B is precharged while the other bank is accessed in order that the banks A and B are alternately accessed. Fast frame access is accomplished.

摘要翻译： 公开了一种具有2岸（银行A和银行B）结构的图像数据存储器。 存储体A只存储偶数场数据，而存储体B仅存储奇数场数据，并且以这样的方式提供由诸如行解码器和列解码器的元件组成的外围电路，使得可以独立于另一个存取存储体。 银行A和B之一被预先充电，而另一个银行被访问，以便银行A和B被交替访问。 完成快速帧访问。

公开(公告)号：US5594701A

公开(公告)日：1997-01-14

申请号：US420875

申请日：1995-04-13

申请人： Hideo Asaka ,  Hiroyuki Yamauchi

发明人： Hideo Asaka ,  Hiroyuki Yamauchi

IPC分类号： G11C8/08 ,  G11C11/408 ,  G11C11/4094 ,  G11C29/02 ,  G11C29/50 ,  G11C8/00 ,  G11C29/00

CPC分类号： G11C11/4094 ,  G11C11/4085 ,  G11C29/02 ,  G11C29/50 ,  G11C8/08 ,  G11C11/401

摘要： Precharge circuits precharge plural pairs of bit lines to a specified potential when no word line is selected (during standby). Pull-down transistors are turned ON when the corresponding word lines are not selected so as to connect the corresponding word lines to a common power source line, which is connected to the ground. In a path connecting the above common power source line to the ground is disposed an impedance changing means for changing the impedance of the path between a value during standby and another valve during operation during which any word line is selected so that the value during standby is set higher than the value during operation. Consequently, during standby, a leakage current (standby current) resulting from a short circuit between a bit line and a word line is reduced.

摘要翻译： 当没有选择字线（待机）时，预充电电路将多对位线预充电到指定的电位。 当对应的字线未被选择时，下拉晶体管导通，以将相应的字线连接到连接到地的公共电源线。 在将上述公共电源线连接到地面的路径中设置有阻抗改变装置，用于改变在待机期间的值与操作期间的另一个阀之间的路径的阻抗，在此期间选择任何字线，使得待机期间的值为 设置高于操作期间的值。 因此，在待机期间，由位线和字线之间的短路引起的漏电流（待机电流）减小。

公开(公告)号：US5508963A

公开(公告)日：1996-04-16

申请号：US209120

申请日：1994-03-11

申请人： Akihiro Sawada ,  Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Shunichi Iwanari ,  Masashi Agata ,  Hirohito Kikukawa ,  Hisakazu Kotani

发明人： Akihiro Sawada ,  Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Shunichi Iwanari ,  Masashi Agata ,  Hirohito Kikukawa ,  Hisakazu Kotani

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/785 ,  G11C29/80 ,  G11C29/808 ,  G11C29/83 ,  G11C29/84 ,  G11C29/846

摘要： N-piece redundant address comparing circuits are individually composed of impedance converting circuits, so that information using redundancy is transmitted as an impedance value. Consequently, even though the N becomes larger as the capacity of a memory becomes larger, a signal line having large capacitance and the node of a redundant judging circuit are not charged or discharged. A high-speed operation can be realized without being affected by the capacitance of the signal line or by the capacitance of the node of the redundant judging circuit.

摘要翻译： N段冗余地址比较电路分别由阻抗转换电路组成，从而使用冗余的信息作为阻抗值传输。 因此，即使当存储器的容量变大时N变大，具有大电容的信号线和冗余判断电路的节点也不被充电或放电。 可以实现高速操作，而不受信号线的电容或冗余判断电路的节点的电容的影响。

公开(公告)号：US08082128B2

公开(公告)日：2011-12-20

申请号：US11358742

申请日：2006-02-22

申请人： Shingo Hori ,  Hiroyuki Yamauchi ,  Tomoyoshi Yabe

发明人： Shingo Hori ,  Hiroyuki Yamauchi ,  Tomoyoshi Yabe

IPC分类号： G06F17/50

CPC分类号： B44F11/00 ,  E04C2002/007 ,  E04C2002/008 ,  G06F17/5004 ,  Y10T428/24479

摘要： The present invention relates to a building material design support system for supporting design of a building material capable of exhibiting a random texture pattern as a whole in a state in which the building materials are installed on a building portion and exhibiting continuity of the texture of adjacent building materials, such building material and a program for use in such building material design support system. More specifically, on a building material, first convex portions #A1L, #A1R, #A2L, #A2R to be arranged next to corresponding first convex portions of an adjacent building material have a prescribed texture common to every building materials, and the second convex portions have randomly arranged textures different from each other on every building material.

摘要翻译： 本发明涉及一种用于支撑建筑材料的设计的建筑材料设计支撑系统，该建筑材料能够在建筑材料安装在建筑物部分上并呈现相邻的质地连续性的状态下整体呈现随机纹理图案 建筑材料，建筑材料和用于此类建筑材料设计支持系统的程序。 更具体地说，在建筑材料上，相邻建筑材料的相应的第一凸部旁边配置的第一凸部＃A1L，＃A1R，＃A2L，＃A2R具有与各建筑材料共同的规定质地，第二凸部 部分在每个建筑材料上随机布置彼此不同的纹理。

公开(公告)号：US07684230B2

公开(公告)日：2010-03-23

申请号：US11476566

申请日：2006-06-29

申请人： Yoshinobu Yamagami ,  Hiroyuki Yamauchi

发明人： Yoshinobu Yamagami ,  Hiroyuki Yamauchi

IPC分类号： G11C11/00 ,  G11C13/00

CPC分类号： G11C11/413

摘要： A semiconductor memory device, including a memory cell including a flip-flop, and a memory cell power supply circuit for supplying a cell power supply voltage to the memory cell, wherein the memory cell power supply circuit supplies a cell power supply voltage in a first period and a different cell power supply voltage in a second period.

摘要翻译： 一种半导体存储器件，包括具有触发器的存储单元和用于向存储单元提供单元电源电压的存储单元电源电路，其中存储单元电源电路将第一单元电源电压 周期和不同的单元电源电压。

公开(公告)号：US07356795B2

公开(公告)日：2008-04-08

申请号：US10935094

申请日：2004-09-08

申请人： Hiroyuki Yamauchi

发明人： Hiroyuki Yamauchi

IPC分类号： G06F17/50

CPC分类号： H01L27/11 ,  G06F17/5045 ,  G06F17/5068 ,  G06F2217/08 ,  G11C11/412 ,  H01L27/1104

摘要： A semiconductor integrated circuit device has a plurality of design patterns composed of circuit elements or wires formed on a substrate. The respective finished sizes of the plurality of design patterns have a plurality of minimum size values which differ from one design pattern to another depending on the geometric feature of each of the design patterns.

摘要翻译： 半导体集成电路器件具有由形成在衬底上的电路元件或电线组成的多个设计图案。 根据每个设计图案的几何特征，多个设计图案的各个成品尺寸具有多个不同于一种设计图案的最小尺寸值。

公开(公告)号：US20080074913A1

公开(公告)日：2008-03-27

申请号：US11980589

申请日：2007-10-31

申请人： Hiroyuki Yamauchi

发明人： Hiroyuki Yamauchi

IPC分类号： G11C5/02 ,  G06F17/50

CPC分类号： H01L27/11 ,  G06F17/5045 ,  G06F17/5068 ,  G06F2217/08 ,  G11C11/412 ,  H01L27/1104

摘要： A semiconductor integrated circuit device has a plurality of design patterns composed of circuit elements or wires formed on a substrate. The respective finished sizes of the plurality of design patterns have a plurality of minimum size values which differ from one design pattern to another depending on the geometric feature of each of the design patterns.

公开(公告)号：US07276939B2

公开(公告)日：2007-10-02

申请号：US10542727

申请日：2003-01-20

申请人： Takayuki Noto ,  Tomoru Sato ,  Hiroyuki Yamauchi

发明人： Takayuki Noto ,  Tomoru Sato ,  Hiroyuki Yamauchi

IPC分类号： H03K19/0175

CPC分类号： H04L25/0278 ,  H03K5/086 ,  H03K17/08142 ,  H03K17/164 ,  H03K17/167 ,  H03K19/0005 ,  H04L25/0292

摘要： A semiconductor integrated circuit includes an input circuit for taking in signals and an output circuit for outputting signals. The input circuit is so set that the input impedance during input signal transition is lower than the input impedance on other occasions than input signal transition. The output circuit is so set that the driving force during the second half of signal transition is lower than the driving force during the first half of transition. Such setting that the input impedance during input signal transition is lower than the input impedance on other occasions than input signal transition reduces reflected waves during input signal transition. Such setting that the driving force during the second half of signal transition is lower than the driving force during the first half of transition suppresses production of reflected waves during the second half of signal transition. Thus, the necessity for external components, such as damping resistors and terminator resistors, for impedance matching is obviated.

摘要翻译： 半导体集成电路包括用于接收信号的输入电路和用于输出信号的输出电路。 输入电路设置为输入信号转换期间的输入阻抗低于输入信号转换时的输入阻抗。 输出电路被设定为使得信号转换的后半段的驱动力低于转换前半部分的驱动力。 在输入信号转换期间，输入信号转换期间的输入阻抗低于输入阻抗，在其他情况下比输入信号转换减少反射波。 在信号转换的后半期间的驱动力比转换的前半部分的驱动力低的设定在信号转换的后半期间抑制了反射波的产生。 因此，消除了用于阻抗匹配的诸如阻尼电阻器和终端电阻器的外部组件的必要性。

公开(公告)号：US20070193160A1

公开(公告)日：2007-08-23

申请号：US11657730

申请日：2007-01-25

申请人： Hiroyuki Yamauchi ,  Tomoyoshi Yabe

发明人： Hiroyuki Yamauchi ,  Tomoyoshi Yabe

IPC分类号： E04F15/00

CPC分类号： E04F13/0871 ,  B42D15/00 ,  B44C5/04 ,  E04F13/0826 ,  E04F13/0892

摘要： In a building board having a designed surface with pattern convex portions, and upper and lower shiplap portions, both of which are formed in the end portion of the designed surface, a printing extension portion is formed in the lower shiplap1 portion, and the printing extension portion is printed in such a way that the extension portion and the pattern convex portion are continuously formed.

摘要翻译： 在具有带有图案凸部的设计表面的建筑板以及两个形成在设计表面的端部中的上部和下部遮光部分的情况下，印刷延伸部分形成在下部shiplap1部分中，并且印刷延伸部 部分以连续形成延伸部分和图案凸出部分的方式印刷。