公开(公告)号：US20220310610A1

公开(公告)日：2022-09-29

申请号：US17213144

申请日：2021-03-25

Applicant: Intel Corporation

Inventor： Abhishek A. SHARMA ,  Willy RACHMADY ,  Cheng-Ying HUANG ,  Gilbert DEWEY ,  Rajat PAUL

IPC: H01L27/108 ,  H01L49/02 ,  H01L27/01 ,  H01L23/522 ,  H01L29/786

Abstract: Thin-film transistors and MIM capacitors in exclusion zones are described. In an example, an integrated circuit structure includes a semiconductor substrate having a zone with metal oxide semiconductor (MOS) transistors therein, and having a zone that excludes MOS transistors. A back-end-of-line (BEOL) structure is above the semiconductor substrate. A thin-film transistor (TFT) and/or a metal-insulator-metal (MIM) capacitor is in the BEOL structure. The TFT and/or MIM capacitor is vertically over the zone that excludes MOS transistors.

公开(公告)号：US20220140076A1

公开(公告)日：2022-05-05

申请号：US17576765

申请日：2022-01-14

Applicant: Intel Corporation

Inventor： Cheng-Ying HUANG ,  Tahir GHANI ,  Jack KAVALIEROS ,  Anand MURTHY ,  Harold KENNEL ,  Gilbert DEWEY ,  Matthew METZ ,  Willy RACHMADY ,  Sean MA ,  Nicholas MINUTILLO

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/205 ,  H01L29/417 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device having a channel area including a channel III-V material, and a source area including a first portion and a second portion of the source area. The first portion of the source area includes a first III-V material, and the second portion of the source area includes a second III-V material. The channel III-V material, the first III-V material and the second III-V material may have a same lattice constant. Moreover, the first III-V material has a first bandgap, and the second III-V material has a second bandgap, the channel III-V material has a channel III-V material bandgap, where the channel material bandgap, the second bandgap, and the first bandgap form a monotonic sequence of bandgaps. Other embodiments may be described and/or claimed.

公开(公告)号：US20220115372A1

公开(公告)日：2022-04-14

申请号：US17555296

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Aaron LILAK ,  Patrick MORROW ,  Gilbert DEWEY ,  Willy RACHMADY ,  Rishabh MEHANDRU

IPC: H01L27/06 ,  H01L29/78 ,  H01L29/06 ,  H01L27/02 ,  H01L23/522 ,  H01L21/8234 ,  H01L21/822

Abstract: Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a lower device layer that includes a first transistor structure, an upper device layer above the lower device layer including a second transistor structure, and an isolation wall that extends between the upper device layer and the lower device layer. The isolation wall may be in contact with an edge of a first gate structure of the first transistor structure and an edge of a second gate structure of the second transistor structure, and may have a first width to the edge of the first gate structure at the lower device layer, and a second width to the edge of the second gate structure at the upper device layer. The first width may be different from the second width. Other embodiments may be described and/or claimed.

公开(公告)号：US20220102521A1

公开(公告)日：2022-03-31

申请号：US17033471

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Nazila HARATIPOUR ,  Siddharth CHOUKSEY ,  Jack T. KAVALIEROS ,  Jitendra Kumar JHA ,  Matthew V. METZ ,  Mengcheng LU ,  Anand S. MURTHY ,  Koustav GANGULY ,  Ryan KEECH ,  Glenn A. GLASS ,  Arnab SEN GUPTA

IPC: H01L29/45 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/08 ,  H01L29/78 ,  H01L21/285 ,  H01L29/66

Abstract: Low resistance approaches for fabricating contacts, and semiconductor structures having low resistance metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor structure above a substrate. A gate electrode is over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure. A first semiconductor source or drain structure is at a first end of the channel region at a first side of the gate electrode. A second semiconductor source or drain structure is at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end. A source or drain contact is directly on the first or second semiconductor source or drain structure, the source or drain contact including a barrier layer and an inner conductive structure.

公开(公告)号：US20220028972A1

公开(公告)日：2022-01-27

申请号：US17493695

申请日：2021-10-04

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Cheng-Ying HUANG ,  Matthew V. METZ ,  Nicholas G. MINUTILLO ,  Sean T. MA ,  Anand S. MURTHY ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Gilbert DEWEY

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/205 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. A gate structure contacts the top surface of the body. A source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).

公开(公告)号：US20210265482A1

公开(公告)日：2021-08-26

申请号：US17239439

申请日：2021-04-23

Applicant: INTEL CORPORATION

Inventor： Gilbert DEWEY ,  Mark L. DOCZY ,  Suman DATTA ,  Justin K. BRASK ,  Matthew V. METZ

IPC: H01L29/51 ,  H01L21/8234 ,  H01L29/49 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66

Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.

公开(公告)号：US20210074703A1

公开(公告)日：2021-03-11

申请号：US16772101

申请日：2018-03-22

Applicant: Intel Corporation

Inventor： Cory E. WEBER ,  Haorld W. KENNEL ,  Willy RACHMADY ,  Gilbert DEWEY

IPC: H01L27/092 ,  H01L27/12 ,  H01L21/8258

Abstract: Semiconductor nanowire devices having (111)-plane channel sidewalls and methods of fabricating semiconductor nanowire devices having (111)-plane channel sidewalls are described. For example, an integrated circuit structure includes a first semiconductor device including a plurality of vertically stacked nanowires disposed above a substrate, each of the nanowires comprising a discrete channel region having lateral sidewalls along a carrier transport direction. The integrated circuit structure also includes a second semiconductor device including a semiconductor fin disposed above the substrate, the semiconductor fin having a channel region with a top and side surfaces, the channel region having lateral sidewalls along a carrier transport direction.

公开(公告)号：US20210057413A1

公开(公告)日：2021-02-25

申请号：US16954126

申请日：2018-03-28

Applicant: Gilbert DEWEY ,  Ravi PILLARISETTY ,  Jack T. KAVALIEROS ,  Aaron D. LILAK ,  Willy RACHMADY ,  Rishabh MEHANDRU ,  Kimin JUN ,  Anh PHAN ,  Hui Jae YOO ,  Patrick MORROW ,  Cheng-Ying HUANG ,  Matthew V. METZ ,  Intel Corporation

Inventor： Gilbert DEWEY ,  Ravi PILLARISETTY ,  Jack T. KAVALIEROS ,  Aaron D. LILAK ,  Willy RACHMADY ,  Rishabh MEHANDRU ,  Kimin JUN ,  Anh PHAN ,  Hui Jae YOO ,  Patrick MORROW ,  Cheng-Ying HUANG ,  Matthew V. METZ

IPC: H01L27/092 ,  H01L21/822 ,  H01L29/08 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/06 ,  H01L29/66 ,  H01L29/06

Abstract: An integrated circuit structure comprises a lower device layer that includes a first structure comprising a plurality of PMOS transistors. An upper device layer is formed on the lower device layer, wherein the upper device layer includes a second structure comprising a plurality of NMOS transistors having a group III-V material source/drain region.

公开(公告)号：US20210050455A1

公开(公告)日：2021-02-18

申请号：US17074251

申请日：2020-10-19

Applicant: Intel Corporation

Inventor： Van H. LE ,  Gilbert DEWEY ,  Rafael RIOS ,  Jack T. KAVALIEROS ,  Marko RADOSAVLJEVIC ,  Kent E. MILLARD ,  Marc C. FRENCH ,  Ashish AGRAWAL ,  Benjamin CHU-KUNG ,  Ryan E. ARCH

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L29/24 ,  H01L29/40 ,  H01L29/49

Abstract: Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and source and drain regions formed over the substrate. According to an embodiment, an IGZO layer may be formed above the substrate and may be electrically coupled to the source region and the drain region. Further embodiments include a gate electrode that is separated from the IGZO layer by a gate dielectric. In an embodiment, the gate dielectric contacts more than one surface of the IGZO layer. In one embodiment, the IGZO transistor is a finfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.

公开(公告)号：US20200227533A1

公开(公告)日：2020-07-16

申请号：US16629555

申请日：2017-09-26

Applicant: Intel Corporation

Inventor： Sean T. MA ,  Willy RACHMADY ,  Gilbert DEWEY ,  Cheng-Ying HUANG ,  Dipanjan BASU

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/20 ,  H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/775

Abstract: Group III-V semiconductor devices having dual workfunction gate electrodes and their methods of fabrication are described. In an example, an integrated circuit structure includes a gallium arsenide layer on a substrate. A channel structure is on the gallium arsenide layer. The channel structure includes indium, gallium and arsenic. A source structure is at a first end of the channel structure and a drain structure is at a second end of the channel structure. A gate structure is over the channel structure, the gate structure having a first workfunction material laterally adjacent a second workfunction material. The second workfunction material has a different workfunction than the first workfunction material.