公开(公告)号：US20210028094A1

公开(公告)日：2021-01-28

申请号：US17069421

申请日：2020-10-13

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Min Suet Lim ,  Tin Poay Chuah

IPC: H01L23/498 ,  H05K1/18 ,  H05K1/14 ,  H05K3/36 ,  H01L23/538 ,  H05K3/46

Abstract: To address the issue of shrinking volume that can be allocated for electrical components, a system can use an interposer with a flexible portion. A first portion of the interposer can electrically connect to a top side of a motherboard. A flexible portion of the interposer, adjacent to the first portion, can wrap around an edge of the motherboard. A peripheral portion of the interposer, adjacent to the flexible portion, can electrically connect to a bottom side of the motherboard. The peripheral portion can be flexible or rigid. The interposer can define a cavity that extends through the first portion of the interposer. A chip package can electrically connect to the first portion of the interposer. The chip package can be coupled to at least one electrical component that extends into the cavity when the chip package is connected to the interposer.

公开(公告)号：US10796999B2

公开(公告)日：2020-10-06

申请号：US16284218

申请日：2019-02-25

Applicant: Intel Corporation

Inventor： Boon Ping Koh ,  Eng Huat Goh ,  Jiun Hann Sir ,  Khang Choong Yong ,  Min Suet Lim ,  Wil Choon Song

IPC: H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor apparatus includes a floating-bridge interconnect that couples two semiconductive devices that are arranged across a middle semiconductive device. The floating-bridge interconnect can be semiconductive material such as a silicon bridge, or it can be an organic bridge. Computing functions required in one of the two semiconductive devices can be off-loaded to any of the floating-bridge interconnect or the other of the two semiconductive devices.

公开(公告)号：US20200137886A1

公开(公告)日：2020-04-30

申请号：US16565639

申请日：2019-09-10

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Eng Huat Goh ,  Jackson Chung Peng Kong ,  Khang Choong Yong ,  Min Suet Lim

IPC: H05K1/03 ,  H05K1/11 ,  H05K3/46 ,  H05K3/40

Abstract: To overcome the problem of the fiber weave effect desynchronizing differential signals in a pair of traces of approximately the same length in a printed circuit board, the pair of traces can be routed to traverse largely parallel paths that are above one another in the printed circuit board. The material between the paths can include weaved fiber bundles. The material on opposite sides of the paths, surrounding the pair of traces and the weaved fiber bundles, can include resin-rich material. As a result, the pair of traces are directly adjacent to the same materials, which can allow signals in the traces to propagate at the same speed, and prevent desynchronization of differential signals traversing the paths. The path length difference associated with traversing to different depths can be compensated with a relatively small in-plane diagonal jog of one of the traces.

公开(公告)号：US20200006204A1

公开(公告)日：2020-01-02

申请号：US16423715

申请日：2019-05-28

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Min Suet Lim ,  Tin Poay Chuah

IPC: H01L23/498 ,  H05K1/18 ,  H05K1/14 ,  H05K3/46 ,  H05K3/36 ,  H01L23/538

Abstract: To address the issue of shrinking volume that can be allocated for electrical components, a system can use an interposer with a flexible portion. A first portion of the interposer can electrically connect to a top side of a motherboard. A flexible portion of the interposer, adjacent to the first portion, can wrap around an edge of the motherboard. A peripheral portion of the interposer, adjacent to the flexible portion, can electrically connect to a bottom side of the motherboard. The peripheral portion can be flexible or rigid. The interposer can define a cavity that extends through the first portion of the interposer. A chip package can electrically connect to the first portion of the interposer. The chip package can be coupled to at least one electrical component that extends into the cavity when the chip package is connected to the interposer.

公开(公告)号：US10515912B2

公开(公告)日：2019-12-24

申请号：US15713660

申请日：2017-09-24

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Jiun Hann Sir ,  Eng Huat Eh Goh ,  Mooi Ling Chang

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/768 ,  H01L23/498 ,  H01L23/31 ,  H01L23/48

Abstract: Substrateless integrated circuit (IC) packages having a die with direct diagonal connections, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, an IC package may include: a die having a face with a plurality of contacts thereon, a dielectric layer in contact with the face, and a conductive pathway extending diagonally through the dielectric layer and coupling to an individual contact of the plurality of contacts on the die. In some embodiments, a conductive pathway may fan out to translate the contacts from a more dense layout to a less dense layout. In some embodiments, a conductive pathway may fan in to translate the contacts from a less dense layout to a more dense layout. In some embodiments, the dielectric layer and the conductive pathway may extend beyond the footprint of the die on one or more edges.

公开(公告)号：US20190229057A1

公开(公告)日：2019-07-25

申请号：US16329080

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Bok Eng Cheah ,  Min Suet Lim ,  Jackson Chung Peng Kong

IPC: H01L23/538 ,  H01L25/065

Abstract: A system in package device includes an overpass die on a package substrate and the overpass die includes a recess on the back side in order to straddle a landed die also on the package substrate. The recess is bounded by at least two overpass walls. Communication between the dice is done with a through-silicon via and communication between the overpass die and the package substrate is also done with a through-silicon via.

公开(公告)号：US10317938B2

公开(公告)日：2019-06-11

申请号：US14604531

申请日：2015-01-23

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Khai Ern See ,  Damien Weng Kong Chong ,  Min Suet Lim ,  Ping Ping Ooi ,  Chu Aun Lim ,  Jimmy Huat Since Huang ,  Poh Tat Oh ,  Teong Keat Beh ,  Jackson Chung Peng Kong ,  Fern Nee Tan ,  Jenn Chuan Cheng

IPC: G06F1/16 ,  H05K1/18 ,  G06F1/18 ,  G06F13/38

Abstract: Embodiments are generally directed to an apparatus utilizing computer on package construction. An embodiment of a computer includes a substrate; one or more semiconductor devices, the one or more semiconductor devices being direct chip attached to the substrate, the one or more semiconductor devices including a central processing unit (CPU); and one or more additional components installed on the substrate, wherein the computer excludes I/O components.

公开(公告)号：US10297541B2

公开(公告)日：2019-05-21

申请号：US15355961

申请日：2016-11-18

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Mooi Ling Chang ,  Eng Huat Goh ,  Say Thong Tony Tan ,  Tin Poay Chuah

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538

Abstract: Microelectronic devices having a multiple-component substrate assembly. A primary supports one or more integrated circuits, and an auxiliary substrate is coupled to, and makes electrical connections with, the primary substrate. The primary substrate will define a pinout for some or all contacts of the integrated circuit, and the auxiliary substrate will provide an additional pinout option. Different configurations of a single primary substrate may be adapted to different applications through use of different configurations of auxiliary substrates.

公开(公告)号：US10256213B2

公开(公告)日：2019-04-09

申请号：US14964972

申请日：2015-12-10

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Min Suet Lim ,  Jiun Hann Sir

IPC: H01L23/02 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L25/065 ,  H01L25/00 ,  H01L27/108 ,  H01L23/31 ,  H01L25/10 ,  H01L25/18

Abstract: A computer memory module can include a molded layer disposed on a DRAM substrate. The molded layer can encapsulate a DRAM die and wire bonds that connect the DRAM die to the DRAM substrate, and can be shaped to include at least one cavity having a footprint sized to accommodate a system on chip (SOC) die. The DRAM module can attach to an SOC package so that the SOC die and the DRAM die are both positioned between the DRAM substrate and the SOC package, the DRAM substrate can form its electrical connections on only one side of the DRAM substrate, and the SOC die can fit at least partially into the cavity in the molded layer. This can reduce a package Z-height, compared to conventional DRAM packages in which the SOC die and the DRAM die are positioned on opposite sides of the DRAM substrate.

公开(公告)号：US10163777B2

公开(公告)日：2018-12-25

申请号：US15476905

申请日：2017-03-31

Applicant: INTEL CORPORATION

Inventor： Seok Ling Lim ,  Eng Huat Goh ,  Hoay Tien Teoh ,  Jenny Shio Yin Ong ,  Jia Yan Go ,  Jiun Hann Sir ,  Min Suet Lim

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/043

Abstract: Interconnects for semiconductor packages are described. An apparatus may comprise a decoupling capacitor on a logic board, and a conductive interconnect element on the logic board, the conductive interconnect element to connect the decoupling capacitor on the logic board to a power conductor comprising a power pad of a semiconductor package, the conductive interconnect element at a different layer than a ground-potential layer of the logic board. Other embodiments are described and claimed.