公开(公告)号：US07132339B2

公开(公告)日：2006-11-07

申请号：US11007843

申请日：2004-12-09

申请人： Andres Bryant ,  Mark D. Jaffe

发明人： Andres Bryant ,  Mark D. Jaffe

IPC分类号： H01L21/36 ,  H01L21/38

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66772 ,  H01L29/66795

摘要： An improved transistor structure that decreases source/drain (S/D) resistance without increasing gate-to-S/D capacitance, thereby increasing device operation. S/D structures are formed into recesses formed on a semiconductor wafer through a semiconductor layer and a first layer of a buried insulator having at least two layers. A body is formed from the semiconductor layer situated between the recesses, and the body comprises a top body surface and a bottom body surface that define a body thickness. Top portions of the S/D structures are within and abut the body thickness. An improved method for forming the improved transistor structure is also described and comprises: forming recesses through a semiconductor layer and a first layer of a buried insulator so that a body is situated between the recesses; and forming S/D structures into the recesses so that top portions of the S/D structures are within and abut a body thickness.

公开(公告)号：US06943405B2

公开(公告)日：2005-09-13

申请号：US10604206

申请日：2003-07-01

申请人： Andres Bryant ,  William F. Clark, Jr. ,  David M. Fried ,  Mark D. Jaffe ,  Edward J. Nowak ,  John J. Pekarik ,  Christopher S. Putnam

发明人： Andres Bryant ,  William F. Clark, Jr. ,  David M. Fried ,  Mark D. Jaffe ,  Edward J. Nowak ,  John J. Pekarik ,  Christopher S. Putnam

IPC分类号： H01L21/308 ,  H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L21/00 ,  H01L29/76

CPC分类号： H01L21/84 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823821 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/785 ,  Y10S438/947

摘要： A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin, and a second-type of FinFET which includes a second fin running parallel to the first fin. The invention also has an insulator fin positioned between the source/drain regions of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin and the second fin, such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The first fin and the second fin have approximately the same width.

摘要翻译： 公开了利用互补翅片型场效应晶体管（FinFET）的集成电路结构的方法和结构。 本发明具有包括第一鳍片的第一类型的FinFET和包括与第一鳍片平行的第二鳍片的第二类型的FinFET。 本发明还具有位于第一第一类型FinFET的源极/漏极区域和第二类型FinFET之间的绝缘体鳍片。 绝缘体鳍片具有与第一鳍片和第二鳍片大致相同的宽度尺寸，使得第一类型的FinFET和第二类型的FinFET之间的间隔大致等于一个鳍片的宽度。 本发明还具有形成在第一类型FinFET和第二类型FinFET的沟道区上的公共栅极。 栅极包括与第一类型的FinFET相邻的第一杂质掺杂区域和与第二类型的FinFET相邻的第二杂质掺杂区域。 第一杂质掺杂区域和第二杂质掺杂区域之间的差异为栅极提供与第一类型FinFET和第二类型FinFET之间的差异有关的不同功函数。 第一鳍片和第二鳍片具有大致相同的宽度。

公开(公告)号：US08741739B2

公开(公告)日：2014-06-03

申请号：US13342697

申请日：2012-01-03

申请人： Alan B. Botula ,  Mark D. Jaffe ,  Alvin J. Joseph

发明人： Alan B. Botula ,  Mark D. Jaffe ,  Alvin J. Joseph

IPC分类号： H01L21/30

CPC分类号： H01L29/16 ,  H01L21/76254

摘要： A semiconductor structure and a method of forming the same. In one embodiment, a method of forming a silicon-on-insulator (SOI) wafer substrate includes: providing a handle substrate; forming a high resistivity material layer over the handle substrate, the high resistivity material layer including one of an amorphous silicon carbide (SiC), a polycrystalline SiC, an amorphous diamond, or a polycrystalline diamond; forming an insulator layer over the high resistivity material layer; and bonding a donor wafer to a top surface of the insulator layer to form the SOI wafer substrate.

摘要翻译： 半导体结构及其形成方法。 在一个实施例中，形成绝缘体上硅（SOI）晶片衬底的方法包括：提供处理衬底; 在所述手柄衬底上形成高电阻率材料层，所述高电阻率材料层包括非晶碳化硅（SiC），多晶SiC，无定形金刚石或多晶金刚石中的一种; 在所述高电阻率材料层上形成绝缘体层; 并将施主晶片接合到绝缘体层的顶表面以形成SOI晶片衬底。

公开(公告)号：US08536035B2

公开(公告)日：2013-09-17

申请号：US13363603

申请日：2012-02-01

申请人： Alan B. Botula ,  Mark D. Jaffe ,  Alvin J. Joseph ,  Kenneth F. McAvey ,  Gerd Pfeiffer ,  Richard A. Phelps

发明人： Alan B. Botula ,  Mark D. Jaffe ,  Alvin J. Joseph ,  Kenneth F. McAvey ,  Gerd Pfeiffer ,  Richard A. Phelps

IPC分类号： H01L21/425

CPC分类号： H01L21/76254

摘要： Silicon-on-insulator (SOI) structures and related methods of forming such structures. In one case, a method includes providing a silicon-on-insulator (SOI) handle substrate having: a substantially uniform resistivity profile along a depth of the handle substrate; and an interstitial oxygen (Oi) concentration of less than approximately 10 parts per million atoms (ppma). The method further includes counter-doping a surface region of the handle, causing the surface region to have a resistivity greater than approximately 3 kOhm-cm, and joining the surface region of the handle substrate with a donor wafer.

摘要翻译： 绝缘体上硅（SOI）结构和形成这种结构的相关方法。 在一种情况下，一种方法包括提供绝缘体上硅（SOI）手柄衬底，其具有：沿着手柄衬底的深度的基本均匀的电阻率分布; 和间隙氧（Oi）浓度小于约10ppm（ppma）。 所述方法还包括对所述手柄的表面区域进行反掺杂，使所述表面区域具有大于约3kOhm-cm的电阻率，并且将所述手柄衬底的表面区域与施主晶片接合。

公开(公告)号：US08233070B2

公开(公告)日：2012-07-31

申请号：US12553457

申请日：2009-09-03

申请人： John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Charles F. Musante

发明人： John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Charles F. Musante

IPC分类号： H04N3/14

CPC分类号： H04N5/37452 ,  H01L27/14609 ,  H04N5/35581 ,  H04N5/3575

摘要： A pixel sensor cell including a column circuit, a design structure for fabricating the pixel sensor cell including the column circuit and a method for operating the pixel sensor cell including the column circuit are predicated upon the measurement of multiple reference data point and signal data point pairs from a floating diffusion at a variable capacitance. The variable capacitance is provided by excluding or including a transfer gate transistor capacitance in addition to a floating diffusion capacitance. Such a variable capacitance provides variable dynamic ranges for the pixel sensor cell including the column circuit.

摘要翻译： 包括列电路的像素传感器单元，用于制造包括列电路的像素传感器单元的设计结构和用于操作包括列电路的像素传感器单元的方法基于多个参考数据点和信号数据点对的测量 从可变电容的浮动扩散。 通过排除或包括传输栅极晶体管电容以及浮动扩散电容来提供可变电容。 这种可变电容为包括列电路的像素传感器单元提供了可变的动态范围。

公开(公告)号：US20120038811A1

公开(公告)日：2012-02-16

申请号：US13283819

申请日：2011-10-28

申请人： John J. Ellis-Monaghan ,  Mark D. Jaffe

发明人： John J. Ellis-Monaghan ,  Mark D. Jaffe

IPC分类号： H04N5/335 ,  H01L27/148

CPC分类号： H04N5/361 ,  H04N5/359

摘要： The image qualify of an image frame from a CMOS image sensor array operated in global shutter mode may be enhanced by dispersing or randomizing the noise introduced by leakage currents from floating drains among the rows of the image frame. Further, the image quality may be improved by accounting for time dependent changes in the output of dark pixels in dark pixel rows or dark pixel columns. In addition, voltage and time dependent changes in the output of dark pixels may also be measured to provide an accurate estimate of the noise introduced to the charge held in the floating drains. Such methods may be employed individually or in combination to improve the quality of the image.

摘要翻译： 来自在全球快门模式下操作的CMOS图像传感器阵列的图像帧的图像限定可以通过将来自浮动排水口的泄漏电流引入的噪声分散或随机化在图像帧的行中来增强。 此外，通过考虑暗像素行或暗像素列中的暗像素的输出中的时间依赖性变化，可以提高图像质量。 此外，还可以测量暗像素的输出中的电压和时间相关的变化，以提供引入到浮动排水管中的电荷的噪声的准确估计。 这样的方法可以单独使用或组合使用以提高图像的质量。

公开(公告)号：US20110279399A1

公开(公告)日：2011-11-17

申请号：US12779994

申请日：2010-05-14

申请人： Brent A. Anderson ,  Mark D. Jaffe ,  Jed H. Rankin

发明人： Brent A. Anderson ,  Mark D. Jaffe ,  Jed H. Rankin

IPC分类号： G06F3/045 ,  G06F3/041 ,  G06F3/042 ,  G09G5/00

CPC分类号： G06F3/042 ,  G06F3/041 ,  G06F3/0421 ,  G06F3/044 ,  G06F2203/04109

摘要： Disclosed herein are embodiments of an interface device (e.g., a display, touchpad, touchscreen display, etc.) with integrated power collection functions. In one embodiment, a solar cell or solar cell array can be located within a substrate at a first surface and an array of interface elements can also be located within the substrate at the first surface such that portions of the solar cell(s) laterally surround the individual interface elements or groups thereof. In another embodiment, a solar cell or solar cell array can be located within the substrate at a first surface and an array of interface elements can be located within the substrate at a second surface opposite the first surface (i.e., opposite the solar cell or solar cell array). In yet another embodiment, an array of diodes, which can function as either solar cells or sensing elements, can be within a substrate at a first surface and can be wired to allow for selective operation in either a power collection mode or sensing mode.

摘要翻译： 这里公开了具有集成的功率收集功能的接口设备（例如，显示器，触摸板，触摸屏显示器等）的实施例。 在一个实施例中，太阳能电池或太阳能电池阵列可以位于第一表面的衬底内，并且界面元件阵列也可以位于第一表面的衬底内，使得太阳能电池的一部分横向包围 各个接口元件或其组合。 在另一个实施例中，太阳能电池或太阳能电池阵列可以位于第一表面的衬底内，并且界面元件的阵列可以位于衬底内的与第一表面相对的第二表面（即，与太阳能电池或太阳能 单元格阵列）。 在另一个实施例中，可以用作太阳能电池或感测元件的二极管阵列可以在第一表面的衬底内，并且可以被布线以允许在电力收集模式或感测模式中的选择性操作。

公开(公告)号：US07531392B2

公开(公告)日：2009-05-12

申请号：US11276366

申请日：2006-02-27

申请人： John J. Ellis-Monaghan ,  Mark D. Jaffe

发明人： John J. Ellis-Monaghan ,  Mark D. Jaffe

IPC分类号： H01L21/84

CPC分类号： H01L21/84 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/76264 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/045

摘要： The present invention relates to semiconductor-on-insulator (SOI) substrate structures that contain surface semiconductor regions of different crystal orientations located directly on an insulator layer. The present invention also relates to methods for fabricating such SOI substrate structures, by growing an insulator layer directly on a multi-orientation bulk semiconductor substrate that comprises surface semiconductor regions of different crystal orientations located directly on a semiconductor base layer, and removing the semiconductor base layer, thereby forming a multi-orientation SOI substrate structure that comprises surface semiconductor regions of different crystal orientations located directly on the insulator layer.

摘要翻译： 本发明涉及绝缘体上半导体（SOI）衬底结构，其包含直接位于绝缘体层上的不同晶体取向的表面半导体区域。 本发明还涉及制造这种SOI衬底结构的方法，通过直接在多取向体半导体衬底上生长绝缘体层，该绝缘体层包括直接位于半导体基底层上的不同晶体取向的表面半导体区域，以及去除半导体基底 从而形成包括直接位于绝缘体层上的不同晶体取向的表面半导体区域的多取向SOI衬底结构。

公开(公告)号：US07517806B2

公开(公告)日：2009-04-14

申请号：US11186748

申请日：2005-07-21

申请人： Andres Bryant ,  William F. Clark, Jr. ,  David M. Fried ,  Mark D. Jaffe ,  Edward J. Nowak ,  John J. Pekarik ,  Christopher S. Putnam

发明人： Andres Bryant ,  William F. Clark, Jr. ,  David M. Fried ,  Mark D. Jaffe ,  Edward J. Nowak ,  John J. Pekarik ,  Christopher S. Putnam

IPC分类号： H01L21/302

CPC分类号： H01L21/84 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823821 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/785 ,  Y10S438/947

摘要： A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin, and a second-type of FinFET which includes a second fin running parallel to the first fin. The invention also has an insulator fin positioned between the source/drain regions of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin and the second fin, such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The first fin and the second fin have approximately the same width.

摘要翻译： 公开了利用互补翅片型场效应晶体管（FinFET）的集成电路结构的方法和结构。 本发明具有包括第一鳍片的第一类型的FinFET和包括与第一鳍片平行的第二鳍片的第二类型的FinFET。 本发明还具有位于第一第一类型FinFET的源极/漏极区域和第二类型FinFET之间的绝缘体鳍片。 绝缘体鳍片具有与第一鳍片和第二鳍片大致相同的宽度尺寸，使得第一类型的FinFET和第二类型的FinFET之间的间隔大致等于一个鳍片的宽度。 本发明还具有形成在第一类型FinFET和第二类型FinFET的沟道区上的公共栅极。 栅极包括与第一类型的FinFET相邻的第一杂质掺杂区域和与第二类型的FinFET相邻的第二杂质掺杂区域。 第一杂质掺杂区域和第二杂质掺杂区域之间的差异为栅极提供与第一类型FinFET和第二类型FinFET之间的差异有关的不同功函数。 第一鳍片和第二鳍片具有大致相同的宽度。

公开(公告)号：US6063687A

公开(公告)日：2000-05-16

申请号：US837141

申请日：1997-04-14

申请人： Edward W. Sengle ,  Mark D. Jaffe ,  Daniel Nelson Maynard ,  Mark Alan Lavin ,  Eric Jeffrey White ,  John A. Bracchitta

发明人： Edward W. Sengle ,  Mark D. Jaffe ,  Daniel Nelson Maynard ,  Mark Alan Lavin ,  Eric Jeffrey White ,  John A. Bracchitta

IPC分类号： H01L21/762 ,  H01L23/522 ,  H01L21/76

CPC分类号： H01L21/76224 ,  H01L23/5222 ,  H01L2924/0002

摘要： A trench isolation structure for a semiconductor is provided including an isolation ring and an isolation path. The isolation ring surrounds active semiconductor areas and is bordered on the outside by inactive semiconductor area. The isolation path extends from the isolation ring through the inactive semiconductor area. A first level conductor on the isolation path electrically connects or capacitively couples a device in the active semiconductor area to a location on the substrate outside the isolation ring. The isolation path has a configuration derived from the layout of the conductor.

摘要翻译： 提供了一种用于半导体的沟槽隔离结构，包括隔离环和隔离路径。 隔离环围绕有源半导体区域，并且在非活性半导体区域的外部界定。 隔离通道从隔离环延伸穿过非活性半导体区域。 隔离路径上的第一级导体将有源半导体区域中的器件电连接或电容耦合到隔离环外部的衬底上的位置。 隔离路径具有从导体的布局导出的配置。