公开(公告)号：US20130196493A1

公开(公告)日：2013-08-01

申请号：US13363603

申请日：2012-02-01

申请人： Alan B. Botula ,  Mark D. Jaffe ,  Alvin J. Joseph ,  Kenneth F. McAvey ,  Gerd Pfeiffer ,  Richard A. Phelps

发明人： Alan B. Botula ,  Mark D. Jaffe ,  Alvin J. Joseph ,  Kenneth F. McAvey ,  Gerd Pfeiffer ,  Richard A. Phelps

IPC分类号： H01L21/265

CPC分类号： H01L21/76254

摘要： Silicon-on-insulator (SOI) structures and related methods of forming such structures. In one case, a method includes providing a silicon-on-insulator (SOI) handle substrate having: a substantially uniform resistivity profile along a depth of the handle substrate; and an interstitial oxygen (Oi) concentration of less than approximately 10 parts per million atoms (ppma). The method further includes counter-doping a surface region of the handle, causing the surface region to have a resistivity greater than approximately 3 kOhm-cm, and joining the surface region of the handle substrate with a donor wafer.

摘要翻译： 绝缘体上硅（SOI）结构和形成这种结构的相关方法。 在一种情况下，一种方法包括提供绝缘体上硅（SOI）手柄衬底，其具有：沿着手柄衬底的深度的基本均匀的电阻率分布; 和间隙氧（Oi）浓度小于约10ppm（ppma）。 所述方法还包括对所述手柄的表面区域进行反掺杂，使所述表面区域具有大于约3kOhm-cm的电阻率，并且将所述手柄衬底的表面区域与施主晶片接合。

公开(公告)号：US20130168835A1

公开(公告)日：2013-07-04

申请号：US13342697

申请日：2012-01-03

申请人： Alan B. Botula ,  Mark D. Jaffe ,  Alvin J. Joseph

发明人： Alan B. Botula ,  Mark D. Jaffe ,  Alvin J. Joseph

IPC分类号： H01L23/58 ,  H01L21/762

CPC分类号： H01L29/16 ,  H01L21/76254

摘要： A semiconductor structure and a method of forming the same. In one embodiment, a method of forming a silicon-on-insulator (SOI) wafer substrate includes: providing a handle substrate; forming a high resistivity material layer over the handle substrate, the high resistivity material layer including one of an amorphous silicon carbide (SiC), a polycrystalline SiC, an amorphous diamond, or a polycrystalline diamond; forming an insulator layer over the high resistivity material layer; and bonding a donor wafer to a top surface of the insulator layer to form the SOI wafer substrate.

摘要翻译： 半导体结构及其形成方法。 在一个实施例中，形成绝缘体上硅（SOI）晶片衬底的方法包括：提供处理衬底; 在所述手柄衬底上形成高电阻率材料层，所述高电阻率材料层包括非晶碳化硅（SiC），多晶SiC，无定形金刚石或多晶金刚石中的一种; 在所述高电阻率材料层上形成绝缘体层; 并将施主晶片接合到绝缘体层的顶表面以形成SOI晶片衬底。

公开(公告)号：US08741739B2

公开(公告)日：2014-06-03

申请号：US13342697

申请日：2012-01-03

申请人： Alan B. Botula ,  Mark D. Jaffe ,  Alvin J. Joseph

发明人： Alan B. Botula ,  Mark D. Jaffe ,  Alvin J. Joseph

IPC分类号： H01L21/30

CPC分类号： H01L29/16 ,  H01L21/76254

摘要： A semiconductor structure and a method of forming the same. In one embodiment, a method of forming a silicon-on-insulator (SOI) wafer substrate includes: providing a handle substrate; forming a high resistivity material layer over the handle substrate, the high resistivity material layer including one of an amorphous silicon carbide (SiC), a polycrystalline SiC, an amorphous diamond, or a polycrystalline diamond; forming an insulator layer over the high resistivity material layer; and bonding a donor wafer to a top surface of the insulator layer to form the SOI wafer substrate.

摘要翻译： 半导体结构及其形成方法。 在一个实施例中，形成绝缘体上硅（SOI）晶片衬底的方法包括：提供处理衬底; 在所述手柄衬底上形成高电阻率材料层，所述高电阻率材料层包括非晶碳化硅（SiC），多晶SiC，无定形金刚石或多晶金刚石中的一种; 在所述高电阻率材料层上形成绝缘体层; 并将施主晶片接合到绝缘体层的顶表面以形成SOI晶片衬底。

公开(公告)号：US08536035B2

公开(公告)日：2013-09-17

申请号：US13363603

申请日：2012-02-01

申请人： Alan B. Botula ,  Mark D. Jaffe ,  Alvin J. Joseph ,  Kenneth F. McAvey ,  Gerd Pfeiffer ,  Richard A. Phelps

发明人： Alan B. Botula ,  Mark D. Jaffe ,  Alvin J. Joseph ,  Kenneth F. McAvey ,  Gerd Pfeiffer ,  Richard A. Phelps

IPC分类号： H01L21/425

CPC分类号： H01L21/76254

摘要： Silicon-on-insulator (SOI) structures and related methods of forming such structures. In one case, a method includes providing a silicon-on-insulator (SOI) handle substrate having: a substantially uniform resistivity profile along a depth of the handle substrate; and an interstitial oxygen (Oi) concentration of less than approximately 10 parts per million atoms (ppma). The method further includes counter-doping a surface region of the handle, causing the surface region to have a resistivity greater than approximately 3 kOhm-cm, and joining the surface region of the handle substrate with a donor wafer.

摘要翻译： 绝缘体上硅（SOI）结构和形成这种结构的相关方法。 在一种情况下，一种方法包括提供绝缘体上硅（SOI）手柄衬底，其具有：沿着手柄衬底的深度的基本均匀的电阻率分布; 和间隙氧（Oi）浓度小于约10ppm（ppma）。 所述方法还包括对所述手柄的表面区域进行反掺杂，使所述表面区域具有大于约3kOhm-cm的电阻率，并且将所述手柄衬底的表面区域与施主晶片接合。

公开(公告)号：US20130026646A1

公开(公告)日：2013-01-31

申请号：US13193991

申请日：2011-07-29

申请人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Alvin J. Joseph

发明人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Alvin J. Joseph

IPC分类号： H01L21/28 ,  G06F17/50 ,  H01L23/48 ,  H01L21/22 ,  H01L21/265

CPC分类号： H01L21/76898 ,  H01L21/26586 ,  H01L29/732

摘要： A method for forming passivated through wafer vias, passivated through wafer via structures, and passivated through wafer via design structures. The method includes: forming a through wafer via in a semiconductor substrate, the through wafer via comprising an electrical conductor extending from a top of the semiconductor substrate to a bottom surface of the semiconductor substrate; and forming a doped layer abutting all sidewalls of the electrical conductor, the doped layer of a same dopant type as the semiconductor substrate, the concentration of dopant in the doped layer greater than the concentration of dopant in the semiconductor substrate, the doped layer intervening between the electrical conductor and the semiconductor substrate.

摘要翻译： 用于形成钝化的晶片通孔的方法，通过晶片通孔结构钝化，并通过设计结构钝化通过晶片。 该方法包括：在半导体衬底中形成贯穿晶片通孔，所述贯通晶片通孔包括从半导体衬底的顶部延伸到半导体衬底的底表面的电导体; 并且形成邻接电导体的所有侧壁的掺杂层，与半导体衬底相同的掺杂剂类型的掺杂层，掺杂层中掺杂剂的浓度大于半导体衬底中掺杂剂的浓度，掺杂层介于 电导体和半导体衬底。

公开(公告)号：US08492272B2

公开(公告)日：2013-07-23

申请号：US13193991

申请日：2011-07-29

申请人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Alvin J. Joseph

发明人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Alvin J. Joseph

IPC分类号： H01L21/4763 ,  H01L21/04 ,  H01L29/40

CPC分类号： H01L21/76898 ,  H01L21/26586 ,  H01L29/732

摘要： A method for forming passivated through wafer vias, passivated through wafer via structures, and passivated through wafer via design structures. The method includes: forming a through wafer via in a semiconductor substrate, the through wafer via comprising an electrical conductor extending from a top of the semiconductor substrate to a bottom surface of the semiconductor substrate; and forming a doped layer abutting all sidewalls of the electrical conductor, the doped layer of a same dopant type as the semiconductor substrate, the concentration of dopant in the doped layer greater than the concentration of dopant in the semiconductor substrate, the doped layer intervening between the electrical conductor and the semiconductor substrate.

摘要翻译： 用于形成钝化的晶片通孔的方法，通过晶片通孔结构钝化，并通过设计结构钝化通过晶片。 该方法包括：在半导体衬底中形成贯穿晶片通孔，所述贯通晶片通孔包括从半导体衬底的顶部延伸到半导体衬底的底表面的电导体; 并且形成邻接电导体的所有侧壁的掺杂层，与半导体衬底相同的掺杂剂类型的掺杂层，掺杂层中掺杂剂的浓度大于半导体衬底中掺杂剂的浓度，掺杂层介于 电导体和半导体衬底。

公开(公告)号：US09058455B2

公开(公告)日：2015-06-16

申请号：US13354705

申请日：2012-01-20

申请人： James W. Adkisson ,  Panglijen Candra ,  Thomas J. Dunbar ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Anthony K. Stamper ,  Randy L. Wolf

发明人： James W. Adkisson ,  Panglijen Candra ,  Thomas J. Dunbar ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Anthony K. Stamper ,  Randy L. Wolf

IPC分类号： G06F17/50 ,  H01L21/768 ,  H01L23/48 ,  H03H9/64 ,  H01L23/00 ,  H01L27/06 ,  H01L49/02 ,  H01L23/66 ,  H01L25/16

CPC分类号： H01L41/293 ,  G06F17/5063 ,  G06F17/5068 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/24 ,  H01L25/16 ,  H01L27/0694 ,  H01L28/40 ,  H01L41/0815 ,  H01L41/25 ,  H01L2224/03009 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/24145 ,  H01L2225/06548 ,  H03H9/64

摘要： A design structure for an integrated radio frequency (RF) filter on a backside of a semiconductor substrate includes: a device on a first side of a substrate; a radio frequency (RF) filter on a backside of the substrate; and at least one substrate conductor extending from the front side of the substrate to the backside of the substrate and electrically coupling the RF filter to the device.

摘要翻译： 在半导体衬底的背面上的集成射频（RF）滤波器的设计结构包括：在衬底的第一侧上的器件; 在衬底的背面上的射频（RF）滤波器; 以及至少一个衬底导体，其从所述衬底的前侧延伸到所述衬底的所述背面并将所述RF滤波器电耦合到所述器件。

公开(公告)号：US08618588B2

公开(公告)日：2013-12-31

申请号：US12915888

申请日：2010-10-29

申请人： Kristin M. Ackerson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel ,  Robert M. Rassel

发明人： Kristin M. Ackerson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel ,  Robert M. Rassel

IPC分类号： H01L31/062 ,  H01L31/113

CPC分类号： H04N5/238 ,  H01L27/14623 ,  H01L27/14625 ,  H01L27/14685 ,  H04N5/3591

摘要： A method of preventing blooming in a pixel array includes affecting an amount of light that impinges on a photoelectric conversion element by adjusting a transmissivity of an electrochromic element based on an output of the photoelectric conversion element.

摘要翻译： 防止像素阵列中的起霜的方法包括通过基于光电转换元件的输出调节电致变色元件的透射率来影响照射到光电转换元件上的光量。

公开(公告)号：US08440490B2

公开(公告)日：2013-05-14

申请号：US13288686

申请日：2011-11-03

申请人： James W. Adkisson ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Dale J. Pearson ,  Dennis L. Rogers

发明人： James W. Adkisson ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Dale J. Pearson ,  Dennis L. Rogers

IPC分类号： H01L31/18

CPC分类号： H01L27/14643 ,  H01L27/1463 ,  H01L27/14689 ,  H01L31/035281

摘要： A method for manufacturing a pixel sensor cell that includes a photosensitive element having a non-laterally disposed charge collection region. The method includes forming a trench recess in a substrate of a first conductivity type material, and filling the trench recess with a material having second conductivity type material. The second conductivity type material is then diffused out of the filled trench material to the substrate region surrounding the trench to form the non-laterally disposed charge collection region. The filled trench material is removed to provide a trench recess, and the trench recess is filled with a material having a first conductivity type material. A surface implant layer is formed at either side of the trench having a first conductivity type material. A collection region of a trench-type photosensitive element is formed of the outdiffused second conductivity type material and is isolated from the substrate surface.

摘要翻译： 一种制造像素传感器单元的方法，该像素传感器单元包括具有非横向放置的电荷收集区域的感光元件。 该方法包括在第一导电类型材料的衬底中形成沟槽凹槽，并用具有第二导电类型材料的材料填充沟槽凹槽。 然后将第二导电类型材料从填充的沟槽材料扩散到围绕沟槽的衬底区域，以形成非横向布置的电荷收集区域。 去除填充的沟槽材料以提供沟槽凹槽，并且用具有第一导电类型材料的材料填充沟槽凹槽。 表面注入层形成在具有第一导电类型材料的沟槽的任一侧。 沟槽型感光元件的收集区域由向外扩散的第二导电型材料形成，并与衬底表面隔离。

公开(公告)号：US08384690B2

公开(公告)日：2013-02-26

申请号：US12779994

申请日：2010-05-14

申请人： Brent A. Anderson ,  Mark D. Jaffe ,  Jed H. Rankin

发明人： Brent A. Anderson ,  Mark D. Jaffe ,  Jed H. Rankin

IPC分类号： G06F3/041 ,  G06F3/045 ,  H01L31/042

CPC分类号： G06F3/042 ,  G06F3/041 ,  G06F3/0421 ,  G06F3/044 ,  G06F2203/04109

摘要： Disclosed herein are embodiments of an interface device (e.g., a display, touchpad, touchscreen display, etc.) with integrated power collection functions. In one embodiment, a solar cell or solar cell array can be located within a substrate at a first surface and an array of interface elements can also be located within the substrate at the first surface such that portions of the solar cell(s) laterally surround the individual interface elements or groups thereof. In another embodiment, a solar cell or solar cell array can be located within the substrate at a first surface and an array of interface elements can be located within the substrate at a second surface opposite the first surface (i.e., opposite the solar cell or solar cell array). In yet another embodiment, an array of diodes, which can function as either solar cells or sensing elements, can be within a substrate at a first surface and can be wired to allow for selective operation in either a power collection mode or sensing mode.

摘要翻译： 这里公开了具有集成的功率收集功能的接口设备（例如，显示器，触摸板，触摸屏显示器等）的实施例。 在一个实施例中，太阳能电池或太阳能电池阵列可以位于第一表面的衬底内，并且界面元件阵列也可以位于第一表面的衬底内，使得太阳能电池的一部分横向包围 各个接口元件或其组合。 在另一个实施例中，太阳能电池或太阳能电池阵列可以位于第一表面的衬底内，并且界面元件的阵列可以位于衬底内的与第一表面相对的第二表面（即，与太阳能电池或太阳能 单元阵列）。 在另一个实施例中，可以用作太阳能电池或感测元件的二极管阵列可以在第一表面的衬底内，并且可以被布线以允许在电力收集模式或感测模式中的选择性操作。