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101.发明申请METHOD AND APPARATUS FOR CONTROLLING A SELECTABLE VOLTAGE AUDIO POWER OUTPUT STAGE 有权用于控制可选择的电压音频功率输出级的方法和装置公开(公告)号：US20080144861A1
公开(公告)日：2008-06-19
申请号：US11611069
申请日：2006-12-14
IPC分类号： H03F21/00
CPC分类号： H03F1/025
摘要： A method and apparatus for controlling a selectable voltage audio power output stage provides a mechanism for raising the selected power amplifier output voltage in time for the arrival of signal peaks to avoid clipping. Signal peaks may either be delayed by delaying an increase in volume control level or enabling signal compression for a predetermined time period, so that sufficient time is provided for the amplifier power supply to stabilize at a higher operating voltage when an increase of power supply voltage is selected. Alternatively, a signal level may be determined at an upstream source, such as a decoder or filter that provides information in sufficient advance of the arrival of the peaks, and used to control the power supply selection, so that the higher power supply voltage level is selected in advance of arrival of the signal peaks that would otherwise cause clipping at the power amplifier output.
摘要翻译： 用于控制可选择的电压音频功率输出级的方法和装置提供了用于在信号峰值到达时及时提升所选择的功率放大器输出电压以避免削波的机制。 信号峰值可以通过延迟音量控制电平的增加或在预定时间段内启用信号压缩来延迟，使得当电源电压的增加是放大器电源稳定在较高的工作电压时，提供足够的时间 选择。 或者，可以在诸如解码器或滤波器的上游源处确定信号电平，所述解码器或滤波器提供足够高的峰值到达之前的信息，并且用于控制电源选择，使得较高的电源电压电平为 在信号峰值的到达之前选择，否则将在功率放大器输出端造成限幅。
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102.发明授权System-on-chip (SoC) integrated circuit including interleaved delta-sigma analog-to-digital converter (ADC) 有权系统级芯片（SoC）集成电路，包括交错式Δ-Σ模数转换器（ADC）公开(公告)号：US07382300B1
公开(公告)日：2008-06-03
申请号：US11564331
申请日：2006-11-29
IPC分类号： H03M3/00
摘要： A system-on-chip (SoC) integrated circuit including an interleaved delta-sigma analog to digital converter (ADC) provides for reduced noise in the ADC conversions. The ADC is operated intermittently and the balance of the digital circuits forming the system are halted while the conversions take place. The halted portion of the system may include an output low-pass filter of the ADC. The system may include a processor core or other logic having a clock frequency unrelated to the ADC modulator clock frequency that is not otherwise clock-managed to reduce noise induced in the converter output by the operation of the core or other logic.
摘要翻译： 包括交错式Δ-Σ模数转换器（ADC）的片上系统（SoC）集成电路可提供ADC转换中的降低的噪声。 ADC间歇性运行，形成系统的数字电路的平衡在转换发生时停止。 系统的暂停部分可以包括ADC的输出低通滤波器。 该系统可以包括处理器核心或具有与ADC调制器时钟频率无关的时钟频率的其它逻辑，否则不是由时钟管理以便通过核心或其他逻辑的操作来减少在转换器输出中感应的噪声。
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103.发明授权公开(公告)号：US07375666B2
公开(公告)日：2008-05-20
申请号：US11531159
申请日：2006-09-12
申请人： John L. Melanson
发明人： John L. Melanson
IPC分类号： H03M3/00
摘要： A feedback topology delta-sigma modulator having an AC-coupled feedback path reduces signal level in the loop filter, easing linearity requirements and reduces capacitor size requirements for the filter integration stages. The delta-sigma modulator includes a loop filter having multiple integrator stages, a quantizer, and a feedback network providing at least two feedback paths to corresponding integrators in the loop filter. In one aspect, only one of the feedback paths from the quantizer output is DC coupled, and at least one other of the feedback paths is DC-coupled, which reduces the signal levels in the loop filter integrators. In another aspect, at least one of the feedback paths from the quantizer is AC coupled, providing a similar result. The AC feedback path may be provided through a series-connected resistor and capacitor. The DC feedback path may be provided through a resistor, a switched-capacitor network, or may be a quantizer-controlled current source.
摘要翻译： 具有AC耦合反馈路径的反馈拓扑Δ-Σ调制器降低了环路滤波器中的信号电平，减轻了线性度要求并降低了滤波器积分级的电容器尺寸要求。 Δ-Σ调制器包括具有多个积分器级的环路滤波器，量化器和向环路滤波器中的相应积分器提供至少两条反馈路径的反馈网络。 在一个方面，仅来自量化器输出的反馈路径之一是直流耦合的，并且至少另一个反馈路径是直流耦合的，这降低了环路滤波器积分器中的信号电平。 在另一方面，来自量化器的反馈路径中的至少一个被AC耦合，提供类似的结果。 AC反馈路径可以通过串联连接的电阻和电容器来提供。 DC反馈路径可以通过电阻器，开关电容器网络提供，或者可以是量化器控制的电流源。
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104.发明申请公开(公告)号：US20080075152A1
公开(公告)日：2008-03-27
申请号：US11739529
申请日：2007-04-24
申请人： John L. Melanson
发明人： John L. Melanson
IPC分类号： H03D3/24
CPC分类号： H03L7/07 , H03L7/1976
摘要： A hybrid analog/digital phase-lock loop with high-level event synchronization provides a mechanism for generating a low-jitter clock from a timing reference that has a high jitter level and synchronizing the output clock to high-level events. A numerically-controlled analog oscillator provides a clock output and a counter divides the frequency of the clock output to provide input to a digital phase-frequency detector for detecting an on-going phase-frequency difference between the timing reference and the output of the counter. A synchronization circuit detects or receives a high-level event signal, and resets the on-going phase-frequency difference and optionally the counter to synchronize the clock output with the events. The synchronization circuit may have an arming input to enable the synchronization circuit to signal a next event. Another clock output divider may be included to generate a timing reference output, and the other clock divider also reset in response to a detected event.
摘要翻译： 具有高级事件同步的混合模拟/数字锁相环提供了一种从具有高抖动电平并将输出时钟同步到高电平事件的定时参考产生低抖动时钟的机制。 数控模拟振荡器提供时钟输出，并且计数器分频时钟输出的频率，以向数字相位频率检测器提供输入，以检测定时基准和计数器的输出之间的正在进行的相位差 。 同步电路检测或接收高电平事件信号，并重置正在进行的相位差和可选的计数器以使时钟输出与事件同步。 同步电路可以具有使得同步电路能够发出下一个事件的布防输入。 可以包括另一个时钟输出分频器以产生定时参考输出，另一个时钟分频器也响应于检测到的事件而复位。
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公开(公告)号：US07342525B2
公开(公告)日：2008-03-11
申请号：US11385021
申请日：2006-03-20
申请人： Chang Yong Kang , John L. Melanson
发明人： Chang Yong Kang , John L. Melanson
IPC分类号： H03M3/00
CPC分类号： H03H17/0416 , H03H17/0444 , H03M3/422 , H03M3/454 , H03M3/508
摘要： Digital to Analog Conversion and sample conversion blocks are combined in order to reduce hardware and/or computational complexity. A novel DSM design is used to perform sample rate conversion. The DSM may also be used to perform other digital filtering functions, thus providing a single hardware/software technique to perform both functions. The invention includes a method and apparatus for converting input data samples provided at a first sample rate to an analog output signal. Input data samples are converted by a Delta Sigma Modulator (DSM) in a Digital to Analog Converter (DAC) to output data samples, where internal states of the DSM are updated at a second sample rate unequal to the first sample rate. At least one internal state of the DSM s modified to account for the time difference in response to a new input sample arriving at a time different from an update of the internal states of the DSM.
摘要翻译： 数字到模拟转换和采样转换块被组合以便降低硬件和/或计算的复杂性。 采用新颖的DSM设计来执行采样率转换。 DSM也可以用于执行其他数字滤波功能，从而提供单一硬件/软件技术来执行这两个功能。 本发明包括用于将以第一采样率提供的输入数据样本转换为模拟输出信号的方法和装置。 输入数据样本由数模转换器（DAC）中的ΔΣ调制器（DSM）转换以输出数据样本，其中DSM的内部状态以不同于第一采样率的第二采样率更新。 DSM的至少一个内部状态被修改为考虑响应于与DSM的内部状态的更新不同的时间到达的新输入样本的时间差。
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公开(公告)号：US20080048618A1
公开(公告)日：2008-02-28
申请号：US11609894
申请日：2006-12-12
申请人： John L. Melanson
发明人： John L. Melanson
IPC分类号： H02J7/00
CPC分类号： H02J7/0031 , H03K17/063 , H03K17/687 , H03K2217/0018
摘要： A charge-pump biased battery protection circuit provides improved efficiency, reduced power dissipation, and reduced complexity in battery powered circuits. A charge pump is utilized to bias the gate of a single pass transistor such that the voltage between the pass transistor gate and the drain/source terminals of the pass transistor have a magnitude greater than the battery voltage, reducing the voltage drop across the pass transistor. The charge pump may be controlled in conformity with a sensed current through the pass transistor, so that at times of lower current loads, power is conserved. The bulk (body) of the pass transistor can be controlled using a resistor coupling a battery terminal to the bulk and a single switch coupling the bulk to a charger/load connection terminal, permitting a single pass transistor to be used for charging and discharging.
摘要翻译： 电荷泵偏置的电池保护电路提高了电池供电电路的效率，降低了功耗，降低了复杂性。 电荷泵用于偏置单通晶体管的栅极，使得通过晶体管栅极与通过晶体管的漏极/源极端子之间的电压具有大于电池电压的幅度，从而减小了通过晶体管两端的电压降 。 电荷泵可以根据通过传感晶体管的感测电流来控制，使得在较低的电流负载的时候，功率被保存。 可以使用将电池端子耦合到本体的电阻器和将体积耦合到充电器/负载连接端子的单个开关来控制传输晶体管的体（体），从而允许将单通晶体管用于充电和放电。
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107.发明授权Signal processing system with modified delta sigma modulator quantizer output signals to spread harmonic frequencies of pulse width modulator output signals 有权信号处理系统采用改进的ΔΣ调制器量化器输出信号，以扩展脉宽调制器输出信号的谐波频率公开(公告)号：US07327296B1
公开(公告)日：2008-02-05
申请号：US11534417
申请日：2006-09-22
IPC分类号： H03M3/00
摘要： The signal processing system includes a pulse width modulator (PWM) that receives input signals from a delta sigma modulator. The PWM generates an output signal having successive frames of PWM patterns. Modifying loop filter data, such as a loop filter output signal, of the delta sigma modulator modifies a delta-sigma modulator quantizer output signal, which in turn changes the frame-to-frame duty cycles of the pulse width modulator output. PWM patterns corresponding to substantially similar delta sigma modulator input signal levels have substantially identical pulse widths. The signal processing system shifts rising and falling edges of pulse width modulator output signals relative to pulse width modulated signals generated from unmodified signals by a quanta of time greater than any deviation between the pulse widths. The signal processing system shifts pulse edges of PWM patterns to spread the spectrum of intra-channel and inter-channel harmonic frequencies.
摘要翻译： 信号处理系统包括从Δ-Σ调制器接收输入信号的脉宽调制器（PWM）。 PWM产生具有连续的PWM模式帧的输出信号。 修改Δ-Σ调制器的环路滤波器输出信号的环路滤波器数据修改Δ-Σ调制器量化器输出信号，其进而改变脉宽调制器输出的帧到帧占空比。 对应于基本相似的ΔΣ调制器输入信号电平的PWM模式具有基本相同的脉冲宽度。 信号处理系统将脉冲宽度调制器输出信号的上升沿和下降沿相对于从未修改的信号产生的脉冲宽度调制信号偏移大于脉冲宽度之间的任何偏差的时间量。 信号处理系统移位PWM模式的脉冲边沿以扩展通道内和频道间谐波频率的频谱。
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公开(公告)号：US07324025B1
公开(公告)日：2008-01-29
申请号：US11528805
申请日：2006-09-28
申请人： Lei Ding , John L. Melanson , Xiaofan Fei
发明人： Lei Ding , John L. Melanson , Xiaofan Fei
IPC分类号： H03M7/00
CPC分类号： H03H17/0671 , H03H17/0685 , H03M3/344 , H03M3/508
摘要： A non-integer CIC interpolation filter is provided for use in sigma-delta digital-to-analog systems, which realizes non-integer interpolation but eliminates the need for coupling of the integrators in the output domain. The present non-integer interpolation filter provides for more attenuation to all of the aliases of the input signal and has eliminated the need of complex computations.
摘要翻译： 提供了一种用于Σ-Δ数模转换系统的非整数CIC内插滤波器，实现非整数插值，但不需要输出域中的积分器耦合。 目前的非整数插值滤波器为输入信号的所有别名提供了更多的衰减，并且消除了复杂计算的需要。
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109.发明授权公开(公告)号：US07221302B1
公开(公告)日：2007-05-22
申请号：US11312842
申请日：2005-12-20
申请人： John L. Melanson
发明人： John L. Melanson
IPC分类号： H03M3/00
摘要： A delta-sigma modulator coefficient calibration method and apparatus provides for adjustment of the modulator coefficients, and thus the modulator noise transfer function (NTF), in operational environments. A noise signal is injected into the feedback loop of the delta-sigma modulator either before or after the quantizer and the output of the modulator is correlated with the noise signal. The delta-sigma modulator has adjustable coefficients that are adjusted in conformity with the correlator output to achieve a more desirable noise transfer function. The correlator may include a tapped delay line and multiple correlators for simultaneously measuring each modulator coefficient directly, or may include a variable delay and a single correlator for measuring each coefficient sequentially.
摘要翻译： Δ-Σ调制器系数校准方法和装置在操作环境中提供调制器系数以及因此调制器噪声传递函数（NTF）的调整。 噪声信号在量化器之前或之后被注入到Δ-Σ调制器的反馈回路中，并且调制器的输出与噪声信号相关。 Δ-Σ调制器具有根据相关器输出调节的可调系数，以实现更理想的噪声传递函数。 相关器可以包括抽头延迟线和用于同时直接测量每个调制器系数的抽头延迟线和多个相关器，或者可以包括可变延迟和用于依次测量每个系数的单个相关器。
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110.发明授权公开(公告)号：US07209064B1
公开(公告)日：2007-04-24
申请号：US11428210
申请日：2006-06-30
申请人： Johann Gaboriau , John L. Melanson
发明人： Johann Gaboriau , John L. Melanson
IPC分类号： H03M1/82
摘要： The signal processing system includes a pulse width modulator (PWM) that receives a quantizer output signal from a delta sigma modulator. Each quantizer output signal represents one of N quantization levels. For at least one of the quantization levels, the PWM can generate multiple, different PWM patterns. Thus, each quantization level in at least a subset of the N quantization levels is associated with at least two PWM patterns. In at least one embodiment, the subset of quantization levels represents the quantization of low level samples of a quantizer input signal. By associating multiple PWM patterns to at least the subset of the quantization levels, the pulse edges of the PWM patterns in a frame are shifted in time with respect to subsequent PWM patterns, which spreads the spectrum of harmonic frequencies of the PWM output signal. Spreading the spectrum of harmonic frequencies of the PWM output signal can reduce electromagnetic interference (EMI).
摘要翻译： 信号处理系统包括从Δ-Σ调制器接收量化器输出信号的脉宽调制器（PWM）。 每个量化器输出信号表示N个量化级中的一个。 对于至少一个量化级别，PWM可以产生多个不同的PWM模式。 因此，N个量化级的至少一个子集中的每个量化级与至少两个PWM模式相关联。 在至少一个实施例中，量化级的子集表示量化器输入信号的低电平采样的量化。 通过将多个PWM模式与至少量子化级别的子集相关联，帧中的PWM模式的脉冲边缘相对于随后的PWM模式在时间上移位，这扩展了PWM输出信号的谐波频率的频谱。 扩展PWM输出信号的谐波频谱可以减少电磁干扰（EMI）。
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