公开(公告)号：US20090296446A1

公开(公告)日：2009-12-03

申请号：US12476950

申请日：2009-06-02

申请人： Yoshiaki Asao

发明人： Yoshiaki Asao

IPC分类号： G11C5/06 ,  G11C11/00

CPC分类号： G11C5/063 ,  G11C11/1659 ,  G11C11/1673

摘要： A semiconductor memory of an aspect of the present invention including a main bit line, a first and second sub-bit line, a first resistive memory element which has a first terminal being connected with the main bit line, a first select transistor which has one end of a first current path being connected with the second terminal of the first resistive memory element and the other end of the first current path being connected with the first sub-bit line, a second resistive memory element which has a third terminal being connected with the main bit line, and a second select transistor which has one end of a second current path being connected with the fourth terminal of the second resistive memory element and the other end of the second current path being connected with the second sub-bit line.

摘要翻译： 本发明的一个方面的半导体存储器，包括主位线，第一和第二子位线，具有与主位线连接的第一端子的第一电阻性存储元件，具有一个第一选择晶体管的第一选择晶体管 第一电流路径的端部与第一电阻性存储元件的第二端子连接，并且第一电流通路的另一端与第一子位线连接;第二电阻存储器元件，其具有与第 主位线和第二选择晶体管，其具有与第二电阻性存储器元件的第四端子连接的第二电流通路的一端，并且第二电流通路的另一端与第二子位线连接。

公开(公告)号：US20090257274A1

公开(公告)日：2009-10-15

申请号：US12400262

申请日：2009-03-09

申请人： Kiyotaro Itagaki ,  Tsuneo Inaba ,  Yoshihiro Ueda ,  Yoshiaki Asao

发明人： Kiyotaro Itagaki ,  Tsuneo Inaba ,  Yoshihiro Ueda ,  Yoshiaki Asao

IPC分类号： G11C11/16 ,  G11C11/14

CPC分类号： G11C11/5607 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/75 ,  G11C2213/78

摘要： A semiconductor memory device includes n resistance change elements which are arranged in one cell, have a low-resistance state and a high resistance state, are connected in series or parallel, have different resistance values in the same resistance state, and change between the low-resistance state and the high-resistance state under different conditions, and a write circuit which is connected to one end of the n resistance change elements, and applies a pulse current m (1≦m≦n) times to the n resistance change elements during a write operation. Letting Im be a current value of an mth pulse current, condition I1>I2> . . . >Im holds.

摘要翻译： 半导体存储器件包括在一个单元中布置的具有低电阻状态和高电阻状态的n个电阻变化元件串联或并联连接，在相同电阻状态下具有不同的电阻值，并且在低电平 电阻状态和不同条件下的高电阻状态，以及与n个电阻变化元件的一端连接的写入电路，并向n个电阻施加脉冲电流m（1 <= m <= n）次 在写入操作期间更改元素。 令Im为第m个脉冲电流的当前值，条件I1> I2>。 。 。 > Im持有。

公开(公告)号：US20080308887A1

公开(公告)日：2008-12-18

申请号：US11943831

申请日：2007-11-21

申请人： Yoshiaki Asao ,  Takeshi Kajiyama

发明人： Yoshiaki Asao ,  Takeshi Kajiyama

IPC分类号： H01L29/82

CPC分类号： G11C11/16 ,  B82Y10/00 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/79 ,  H01L27/228 ,  H01L27/24

摘要： A semiconductor memory device includes first to third wiring layers formed above a semiconductor substrate, extending in a first direction, and sequentially arranged in a second direction perpendicular to the first direction, a plurality of active areas formed in the semiconductor substrate, and extending in a direction oblique to the first direction, first and second selection transistors formed in each of the active areas, and sharing a source region electrically connected to the second wiring layer, a first magnetoresistive element having one terminal electrically connected to a drain region of the first selection transistor, and the other terminal electrically connected to the first wiring layer, and a second magnetoresistive element having one terminal electrically connected to a drain region of the second selection transistor, and the other terminal electrically connected to the third wiring layer.

摘要翻译： 半导体存储器件包括形成在半导体衬底上的第一至第三布线层，沿第一方向延伸，并且沿垂直于第一方向的第二方向依次布置;形成在半导体衬底中的多个有源区， 形成在每个有源区中的第一和第二选择晶体管，并且共用与第二布线层电连接的源极区;第一磁阻元件，具有与第一选择区的漏极区域电连接的一个端子 晶体管，另一个端子电连接到第一布线层，以及第二磁阻元件，其具有一个端子电连接到第二选择晶体管的漏极区域，另一个端子电连接到第三布线层。

公开(公告)号：US20080265347A1

公开(公告)日：2008-10-30

申请号：US12108093

申请日：2008-04-23

申请人： Masayoshi Iwayama ,  Yoshiaki Asao ,  Takeshi Kajiyama ,  Keiji Hosotani

发明人： Masayoshi Iwayama ,  Yoshiaki Asao ,  Takeshi Kajiyama ,  Keiji Hosotani

IPC分类号： H01L29/82 ,  H01L21/00

CPC分类号： H01L43/08 ,  H01L27/222 ,  H01L43/12

摘要： A magnetoresistive element includes a first stacked structure formed by sequentially stacking a first fixed layer in which a magnetization direction is fixed and a first nonmagnetic layer, a second stacked structure formed on the first stacked structure by sequentially stacking a free layer in which a magnetization direction is changeable, a second nonmagnetic layer, and a second fixed layer in which a magnetization direction is fixed, and a circumferential wall formed in contact with a circumferential surface of the second stacked structure to surround the second stacked structure, and made of an insulator. A circumferential surface of the first stacked structure is substantially perpendicular. The second stacked structure has a tapered shape which narrows upward.

摘要翻译： 磁阻元件包括通过顺序层叠形成磁化方向的第一固定层和第一非磁性层的第一堆叠结构而形成的第一堆叠结构，通过顺序堆叠在第一层叠结构上形成的第二堆叠结构，其中磁化方向 可变化的第二非磁性层和固定有磁化方向的第二固定层，以及与第二堆叠结构的周向表面接触以围绕第二堆叠结构并由绝缘体制成的周壁。 第一堆叠结构的圆周表面基本垂直。 第二堆叠结构具有向上变窄的锥形形状。

公开(公告)号：US20080205126A1

公开(公告)日：2008-08-28

申请号：US12037425

申请日：2008-02-26

申请人： Takeshi Kajiyama ,  Yoshiaki Asao

发明人： Takeshi Kajiyama ,  Yoshiaki Asao

IPC分类号： G11C11/14

CPC分类号： H01L43/08 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1675 ,  H01L27/222 ,  H01L27/228 ,  H01L43/02 ,  H01L43/10

摘要： A magnetic random access memory which is a memory cell array including a magnetoresistive effect element having a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction is reversible, and a non-magnetic layer provided between the fixed layer and the recording layer, wherein all conductive layers in the memory cell array arranged below the magnetoresistive effect element are formed of materials each containing an element selected from a group including W, Mo, Ta, Ti, Zr, Nb, Cr, Hf, V, Co, and Ni.

摘要翻译： 一种磁性随机存取存储器，其是包括具有固定磁化方向的固定层的磁阻效应元件，其磁化方向可逆的记录层和设置在固定层与记录层之间的非磁性层的存储单元阵列 其中，布置在磁阻效应元件下方的存储单元阵列中的所有导电层由各自含有选自包括W，Mo，Ta，Ti，Zr，Nb，Cr，Hf，V，Co和 倪

公开(公告)号：US20080002459A1

公开(公告)日：2008-01-03

申请号：US11609487

申请日：2006-12-12

申请人： Yoshiaki FUKUZUMI ,  Toshihiko Nagase ,  Yoshiaki Asao

发明人： Yoshiaki FUKUZUMI ,  Toshihiko Nagase ,  Yoshiaki Asao

IPC分类号： G11C11/00 ,  G11C11/24

CPC分类号： G11C11/16

摘要： A magnetic memory device includes a magnetization fixed layer provided above a semiconductor substrate surface and having a fixed magnetization direction. A first magnetization free layer is provided above the magnetization fixed layer, has variable magnetization direction, and has an easy magnetization axis extending along a plane intersecting the substrate surface and along a direction neither parallel nor perpendicular to the substrate surface. A second magnetization free layer is provided above the first magnetization free layer, has a magnetization that antiferromagnetically couples with the first magnetization free layer. A first write line is placed above and electrically connected to the second magnetization free layer, and extends in a direction that pierces the plane. A second write line faces the first and/or second magnetization free layer, and extends along the substrate surface and the plane and in a direction perpendicular to the first write line.

摘要翻译： 磁存储器件包括设置在半导体衬底表面上方并且具有固定的磁化方向的磁化固定层。 第一磁化自由层设置在磁化固定层的上方，具有可变的磁化方向，并且具有沿着与衬底表面相交的平面并且沿着不平行或垂直于衬底表面的方向延伸的易磁化轴。 第二磁化自由层设置在第一磁化自由层的上方，具有与第一磁化自由层反铁磁耦合的磁化。 第一写入线被放置在第二磁化自由层的上方并且电连接到第二写入线，并且沿着穿透该平面的方向延伸。 第二写入线面向第一和/或第二磁化自由层，并且沿着衬底表面和平面以及垂直于第一写入线的方向延伸。

公开(公告)号：US20070091673A1

公开(公告)日：2007-04-26

申请号：US11313847

申请日：2005-12-22

申请人： Yoshiaki Asao ,  Akihiro Nitayama

发明人： Yoshiaki Asao ,  Akihiro Nitayama

IPC分类号： G11C11/14

CPC分类号： G11C11/16

摘要： A semiconductor memory device includes a memory cell block including a plurality of memory cells connected in series between first node and second node, the memory cells including a magnetoresistive element and a switching transistor, which are connected in parallel, the magnetoresistive element being a spin injection type and including a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction changes, and a non-magnetic layer interposed between the fixed layer and the recording layer, a bit line connected to the first node via a selection transistor, a word line connected to a gate of the switching transistor, and a write line connected to the second node.

摘要翻译： 半导体存储器件包括存储单元块，其包括串联连接在第一节点和第二节点之间的多个存储器单元，存储单元包括并联连接的磁阻元件和开关晶体管，磁阻元件是自旋注入 并且包括其磁化方向固定的固定层，其磁化方向改变的记录层和介于固定层和记录层之间的非磁性层，经由选择晶体管连接到第一结点的位线， 连接到开关晶体管的栅极的字线和连接到第二节点的写入线。

公开(公告)号：US07091539B2

公开(公告)日：2006-08-15

申请号：US10971096

申请日：2004-10-25

申请人： Yoshiaki Asao

发明人： Yoshiaki Asao

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L43/08 ,  B82Y10/00 ,  H01L27/224 ,  H01L27/228

摘要： A data selection line (write line) is disposed right on a MTJ element. Upper and side surfaces of the data selection line are coated with yoke materials which have a high permeability. The yoke materials are separated from each other by a barrier layer. Similarly, a write word line is disposed right under the MTJ element. The lower and side surfaces of the write word line are also coated with the yoke materials which have the high permeability. The yoke materials on the lower and side surfaces of the write word line are also separated from each other by the barrier layer.

摘要翻译： 数据选择线（写入线）被放置在MTJ元件上。 数据选择线的上表面和侧表面涂覆有磁导率高的磁轭材料。 磁轭材料通过阻挡层彼此分离。 类似地，写字线被布置在MTJ元件的正下方。 写字线的下表面和侧表面也涂有具有高磁导率的磁轭材料。 写字线的下表面和侧表面上的轭材料也通过阻挡层彼此分离。

公开(公告)号：US20060054947A1

公开(公告)日：2006-03-16

申请号：US10989339

申请日：2004-11-17

申请人： Yoshiaki Asao ,  Hiroaki Yoda

发明人： Yoshiaki Asao ,  Hiroaki Yoda

IPC分类号： H01L29/94

CPC分类号： H01L43/08 ,  H01L27/222 ,  H01L27/224 ,  H01L27/228 ,  H01L43/12

摘要： A magnetic random access memory includes, a lower electrode, a magnetoresistive element which is arranged above the lower electrode and has side surfaces, and a protective film which covers the side surfaces of the magnetoresistive element, has a same planar shape as the lower electrode, and is formed by one of sputtering, plasma CVD, and ALD.

摘要翻译： 磁性随机存取存储器包括下电极，布置在下电极上方并具有侧表面的磁阻元件和覆盖磁阻元件的侧表面的保护膜具有与下电极相同的平面形状， 并且由溅射，等离子体CVD和ALD之一形成。

公开(公告)号：US06984865B2

公开(公告)日：2006-01-10

申请号：US10847384

申请日：2004-05-18

申请人： Takeshi Kajiyama ,  Tomomasa Ueda ,  Tatsuya Kishi ,  Hisanori Aikawa ,  Masatoshi Yoshikawa ,  Yoshiaki Asao ,  Hiroaki Yoda

发明人： Takeshi Kajiyama ,  Tomomasa Ueda ,  Tatsuya Kishi ,  Hisanori Aikawa ,  Masatoshi Yoshikawa ,  Yoshiaki Asao ,  Hiroaki Yoda

IPC分类号： H01L29/82

CPC分类号： G11C11/16 ,  B82Y10/00 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

摘要： A magnetic random access memory concerning an example of the present invention comprises a magneto resistive element, a first insulating layer which covers side surfaces of the magneto resistive element, a second insulating layer which is arranged on the first insulating layer and has a first groove on the magneto resistive element, a write line which fills the first groove and is connected with the magneto resistive element, and a third insulating layer which is arranged between the first and second insulating layers except a bottom portion of the first groove and has an etching selection ratio with respect to at least the first and second insulating layers.

摘要翻译： 关于本发明的实例的磁性随机存取存储器包括磁阻元件，覆盖磁阻元件的侧表面的第一绝缘层，布置在第一绝缘层上并具有第一凹槽的第二绝缘层 磁阻元件，填充第一沟槽并与磁阻元件连接的写入线以及布置在除了第一沟槽的底部之外的第一和第二绝缘层之间的第三绝缘层，并且具有蚀刻选择 至少相对于第一绝缘层和第二绝缘层。