公开(公告)号：US08941197B2

公开(公告)日：2015-01-27

申请号：US13370075

申请日：2012-02-09

申请人： Takeshi Kajiyama ,  Yoshiaki Asao

发明人： Takeshi Kajiyama ,  Yoshiaki Asao

IPC分类号： H01L27/22 ,  G11C11/16

CPC分类号： H01L43/08 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1675 ,  H01L27/222 ,  H01L27/228 ,  H01L43/02 ,  H01L43/10

摘要： A magnetic random access memory which is a memory cell array including a magnetoresistive effect element having a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction is reversible, and a non-magnetic layer provided between the fixed layer and the recording layer, wherein all conductive layers in the memory cell array arranged below the magnetoresistive effect element are formed of materials each containing an element selected from a group including W, Mo, Ta, Ti, Zr, Nb, Cr, Hf, V, Co, and Ni.

摘要翻译： 一种磁性随机存取存储器，其是包括具有固定磁化方向的固定层的磁阻效应元件，其磁化方向可逆的记录层和设置在固定层与记录层之间的非磁性层的存储单元阵列 其中，布置在磁阻效应元件下方的存储单元阵列中的所有导电层由各自含有选自包括W，Mo，Ta，Ti，Zr，Nb，Cr，Hf，V，Co和 倪

公开(公告)号：US09190453B2

公开(公告)日：2015-11-17

申请号：US14622027

申请日：2015-02-13

申请人： Takashi Nakazawa ,  Yoshiaki Asao ,  Takeshi Kajiyama ,  Kenji Noma

发明人： Takashi Nakazawa ,  Yoshiaki Asao ,  Takeshi Kajiyama ,  Kenji Noma

IPC分类号： H01L43/00 ,  H01L27/00 ,  H01L27/22 ,  H01L43/12 ,  H01L27/24 ,  H01L43/08 ,  H01L43/02 ,  G11C11/16

CPC分类号： H01L27/228 ,  G11C11/161 ,  G11C11/1655 ,  H01L27/2463 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

摘要： According to one embodiment, a magnetic memory including an isolation region with an insulator in a trench is disclosed. The isolation region defines active areas extending in a 1st direction and having 1st and 2nd active areas, an isolation region extending in a 2nd direction perpendicular to the 1st direction exists between the 1st and 2nd active areas. 1st and 2nd word lines extending in the 2nd direction are buried in a surface of semiconductor substrate. 1st and 2nd select transistors connected to the word lines are on the 1st active area. 1st and 2nd variable resistance elements connected to drain regions of the 1st and 2nd select transistors are on the 1st active area.

公开(公告)号：US08829580B2

公开(公告)日：2014-09-09

申请号：US12854724

申请日：2010-08-11

申请人： Kuniaki Sugiura ,  Yoshiaki Asao ,  Takeshi Kajiyama

发明人： Kuniaki Sugiura ,  Yoshiaki Asao ,  Takeshi Kajiyama

IPC分类号： H01L29/82

CPC分类号： H01L27/228 ,  H01L43/08 ,  H01L43/12

摘要： According to one embodiment, a magnetoresistive memory includes first and second contact plugs in a first interlayer insulating film, a lower electrode on the first interlayer insulating film, a magnetoresistive effect element on the lower electrode, and an upper electrode on the magnetoresistive effect element. The lower electrode has a tapered cross-sectional shape in which a dimension of a bottom surface of the lower electrode is longer than a dimension of an upper surface of the lower electrode, one end of the lower electrode is in contact with an upper surface of the first contact plug. The magnetoresistive effect element is provided at a position shifted from a position immediately above the first contact plug in a direction parallel to a surface of the semiconductor substrate.

摘要翻译： 根据一个实施例，磁阻存储器包括第一层间绝缘膜中的第一和第二接触插塞，第一层间绝缘膜上的下电极，下电极上的磁阻效应元件和磁阻效应元件上的上电极。 下电极具有锥形横截面形状，其中下电极的底表面的尺寸比下电极的上表面的尺寸长，下电极的一端与上电极的上表面接触 第一个接触插头。 磁阻效应元件设置在与第一接触插塞正上方的位置在平行于半导体衬底的表面的方向上偏移的位置处。

公开(公告)号：US08111540B2

公开(公告)日：2012-02-07

申请号：US12559335

申请日：2009-09-14

申请人： Yoshiaki Asao ,  Takeshi Kajiyama ,  Tsuneo Inaba

发明人： Yoshiaki Asao ,  Takeshi Kajiyama ,  Tsuneo Inaba

IPC分类号： G11C5/06 ,  G11C5/02 ,  G11C11/00 ,  G11C11/02 ,  G11C11/14 ,  G11C11/15

CPC分类号： G11C11/1659

摘要： A semiconductor memory device includes first and second bit line provided in the same level layer above a semiconductor substrate, a first variable-resistance element disposed under the first bit line, having one terminal connected to one end of a current path of a first MOSFET, a second variable-resistance element disposed under the second bit line, and having one terminal connected to one end of a current path of a second MOSFET, a first interconnect layer connecting the first bit line to the other terminal of the first variable-resistance element, and connecting the first bit line to the other end of the current path of the second MOSFET, and a second interconnect layer connecting the second bit line to the other terminal of the second variable-resistance element, and connecting the second bit line to the other end of the current path of the first MOSFET.

摘要翻译： 半导体存储器件包括设置在半导体衬底上的同一电平层中的第一和第二位线，设置在第一位线下方的第一可变电阻元件，其一端连接到第一MOSFET的电流通路的一端， 第二可变电阻元件，设置在第二位线下方，并且具有连接到第二MOSFET的电流通路的一端的一个端子，将第一位线连接到第一可变电阻元件的另一端子的第一互连层 并且将第一位线连接到第二MOSFET的电流路径的另一端，以及将第二位线连接到第二可变电阻元件的另一端的第二互连层，并将第二位线连接到第二位线 第一个MOSFET的电流通路的另一端。

公开(公告)号：US08058080B2

公开(公告)日：2011-11-15

申请号：US12699721

申请日：2010-02-03

申请人： Takeshi Kajiyama ,  Yoshiaki Asao ,  Minoru Amano ,  Shigeki Takahashi ,  Masayoshi Iwayama ,  Kuniaki Sugiura

发明人： Takeshi Kajiyama ,  Yoshiaki Asao ,  Minoru Amano ,  Shigeki Takahashi ,  Masayoshi Iwayama ,  Kuniaki Sugiura

IPC分类号： H01L21/00 ,  H01L21/20 ,  H01L21/36

CPC分类号： H01L43/12 ,  G11C11/161 ,  H01L27/228

摘要： A magnetic material of a magnetoresistive element is formed on a lower electrode. An upper electrode is formed on the magnetic material. A resist for nano-imprint lithography is formed on the upper electrode. A first pattern or a second pattern is formed in the resist by setting a first template or a second template into contact with the resist and curing the resist. The first template has the first pattern that corresponds to the magnetoresistive element and the lower electrode. The second template has the second pattern that corresponds to the magnetoresistive element and the upper electrode. The magnetic material and the lower electrode are patterned at the same time by using the resist having the first pattern, or the magnetic material and the upper electrode are patterned at the same time by using the resist having the second pattern.

摘要翻译： 磁阻元件的磁性材料形成在下电极上。 在磁性材料上形成上部电极。 在上电极上形成用于纳米压印光刻的抗蚀剂。 通过将第一模板或第二模板与抗蚀剂接触并固化抗蚀剂，在抗蚀剂中形成第一图案或第二图案。 第一模板具有对应于磁阻元件和下电极的第一图案。 第二模板具有对应于磁阻元件和上电极的第二图案。 通过使用具有第一图案的抗蚀剂，同时对磁性材料和下部电极进行图案化，或者通过使用具有第二图案的抗蚀剂同时对磁性材料和上部电极进行图案化。

公开(公告)号：US20110062421A1

公开(公告)日：2011-03-17

申请号：US12700502

申请日：2010-02-04

申请人： Masayoshi Iwayama ,  Yoshiaki Asao ,  Takeshi Kajiyama

发明人： Masayoshi Iwayama ,  Yoshiaki Asao ,  Takeshi Kajiyama

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/42392 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/7613 ,  H01L29/775 ,  H01L29/78696

摘要： First semiconductor layers are in source/drain regions on the semiconductor substrate. A second semiconductor layer comprises first portions on the first semiconductor layers and a second portion in a linear form in a channel region between the source/drain regions. A gate electrode is around the second portion of the second semiconductor layer via an insulating film. A film thickness of the second portion of the second semiconductor layer is smaller than a film thickness of the first portion of the second semiconductor layer.

摘要翻译： 第一半导体层位于半导体衬底上的源/漏区中。 第二半导体层包括在第一半导体层上的第一部分和在源极/漏极区之间的沟道区中线性形式的第二部分。 栅电极经由绝缘膜在第二半导体层的第二部分周围。 第二半导体层的第二部分的膜厚度小于第二半导体层的第一部分的膜厚度。

公开(公告)号：US06927468B2

公开(公告)日：2005-08-09

申请号：US10379915

申请日：2003-03-06

申请人： Hiroaki Yoda ,  Yoshiaki Asao ,  Tomomasa Ueda ,  Junichi Miyamoto ,  Tatsuya Kishi ,  Minoru Amano ,  Takeshi Kajiyama ,  Hisanori Aikawa

发明人： Hiroaki Yoda ,  Yoshiaki Asao ,  Tomomasa Ueda ,  Junichi Miyamoto ,  Tatsuya Kishi ,  Minoru Amano ,  Takeshi Kajiyama ,  Hisanori Aikawa

IPC分类号： G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  H01L29/82

CPC分类号： G11C11/16

摘要： A write line is covered with a yoke material. The recording layer of an MTJ element is exchange-coupled to the yoke material. The total magnetic volume ΣMsi×ti of the recording layer of the MTJ element and a portion of the yoke material that is exchange-coupled to the recording layer is smaller than the magnetic volume ΣMsi′×ti′ of the remaining portion of the yoke material that covers the write line.

摘要翻译： 写线用轭材料覆盖。 MTJ元件的记录层与磁轭材料交换耦合。 MTJ元件的记录层的总磁体体积SigmaMsixti和与记录层交换耦合的磁轭材料的一部分小于磁轭材料的剩余部分的磁体积SigmaMsi'xti' 写行。

公开(公告)号：US08981446B2

公开(公告)日：2015-03-17

申请号：US14018337

申请日：2013-09-04

申请人： Takashi Nakazawa ,  Yoshiaki Asao ,  Takeshi Kajiyama ,  Kenji Noma

发明人： Takashi Nakazawa ,  Yoshiaki Asao ,  Takeshi Kajiyama ,  Kenji Noma

IPC分类号： H01L27/108 ,  H01L21/8244 ,  G11C11/00 ,  H01L43/02 ,  H01L43/12 ,  H01L27/22 ,  G11C11/16

CPC分类号： H01L27/228 ,  G11C11/161 ,  G11C11/1655 ,  H01L27/2463 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

摘要： According to one embodiment, a magnetic memory including an isolation region with an insulator in a trench is disclosed. The isolation region defines active areas extending in a 1st direction and having 1st and 2nd active areas, an isolation region extending in a 2nd direction perpendicular to the 1st direction exists between the 1st and 2nd active areas. 1st and 2nd word lines extending in the 2nd direction are buried in a surface of semiconductor substrate. 1st and 2nd select transistors connected to the word lines are on the 1st active area. 1st and 2nd variable resistance elements connected to drain regions of the 1st and 2nd select transistors are on the 1st active area.

摘要翻译： 根据一个实施例，公开了一种包括在沟槽中具有绝缘体的隔离区的磁存储器。 隔离区域限定在第一方向上延伸并且具有第一和第二有源区域的有源区域，在第一和第二有效区域之间存在沿垂直于第一方向的第二方向延伸的隔离区域。 在第二方向上延伸的第一和第二字线被埋在半导体衬底的表面中。 连接到字线的第一和第二选择晶体管在第一有效区域。 连接到第一和第二选择晶体管的漏极区的第一和第二可变电阻元件在第一有效区上。

公开(公告)号：US08542519B2

公开(公告)日：2013-09-24

申请号：US13035168

申请日：2011-02-25

申请人： Yoshiaki Asao ,  Takeshi Kajiyama ,  Kuniaki Sugiura

发明人： Yoshiaki Asao ,  Takeshi Kajiyama ,  Kuniaki Sugiura

IPC分类号： G11C11/02

CPC分类号： H01L29/82

摘要： According to one embodiment, a semiconductor memory device is disclosed. The device includes MOSFET1 and MOSFET2 arranged in a first direction, variable resistive element (hereafter R1) above MOSFET1 and MOSFET2, a lower end of the R1 being connected to drains of MOSFET1 and MOSFET2, MOSFET3 and MOSFET4 arranged in the first direction, variable resistive element (hereafter R2) above MOSFET3 and MOSFET4, and a lower end of the R2 being connected to drains of MOSFET3 and MOSFET4. The device further includes first wiring line extending in the first direction and connected to sources of MOSFET1 and MOSFET2, second wiring line extending in the first direction and connected to sources of MOSFET3 and MOSFET4, upper electrode connecting upper end of the R1 and upper end of the R2, and third wiring line extending in the first direction and connected to the upper electrode.

摘要翻译： 根据一个实施例，公开了一种半导体存储器件。 该器件包括在第一方向上布置的MOSFET1和MOSFET2，MOSFET1和MOSFET2上方的可变电阻元件（以下称为R1），R1的下端连接到沿第一方向布置的MOSFET1和MOSFET2，MOSFET3和MOSFET4的漏极，可变电阻 元件（以下称为R2），MOSFET3和MOSFET4之上，R2的下端连接到MOSFET3和MOSFET4的漏极。 该器件还包括沿第一方向延伸并连接到MOSFET1和MOSFET2的源极的第一布线，第二布线沿第一方向延伸并连接到MOSFET3和MOSFET4的源极，上电极连接R1的上端和上端 R2和第三布线沿第一方向延伸并连接到上电极。

公开(公告)号：US08314464B2

公开(公告)日：2012-11-20

申请号：US12700502

申请日：2010-02-04

申请人： Masayoshi Iwayama ,  Yoshiaki Asao ,  Takeshi Kajiyama

发明人： Masayoshi Iwayama ,  Yoshiaki Asao ,  Takeshi Kajiyama

IPC分类号： H01L29/78

CPC分类号： H01L29/42392 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/7613 ,  H01L29/775 ,  H01L29/78696

摘要： First semiconductor layers are in source/drain regions on the semiconductor substrate. A second semiconductor layer comprises first portions on the first semiconductor layers and a second portion in a linear form in a channel region between the source/drain regions. A gate electrode is around the second portion of the second semiconductor layer via an insulating film. A film thickness of the second portion of the second semiconductor layer is smaller than a film thickness of the first portion of the second semiconductor layer.

摘要翻译： 第一半导体层位于半导体衬底上的源/漏区中。 第二半导体层包括在第一半导体层上的第一部分和在源极/漏极区之间的沟道区中线性形式的第二部分。 栅电极经由绝缘膜在第二半导体层的第二部分周围。 第二半导体层的第二部分的膜厚度小于第二半导体层的第一部分的膜厚度。