公开(公告)号：US11789519B2

公开(公告)日：2023-10-17

申请号：US17892629

申请日：2022-08-22

Applicant: Micron Technology, Inc.

Inventor： Debra M. Bell ,  Roya Baghi ,  Erica M. Gove ,  Zahra Hosseinimakarem ,  Cheryl M. O'Donnell

IPC: G06F1/3234 ,  G11C16/26 ,  G11C11/56

CPC classification number: G06F1/3275 ,  G11C11/5642 ,  G11C16/26

Abstract: Systems, apparatuses, and methods related to using memory device sensors are described. Some memory system or device types include sensors embedded in their circuitry. For instance, a device can be coupled to a memory device with an embedded sensor. The memory device can transmit the data generated by the embedded sensor using a sensor output coupled to the device. The memory device may generate, based at least in part on a characteristic of a memory device, a signal from a sensor embedded in the memory device and transmit the signal generated by the sensor from the memory device to another device coupled to the memory device.

公开(公告)号：US11748021B2

公开(公告)日：2023-09-05

申请号：US17518164

申请日：2021-11-03

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Debra M. Bell

IPC: G06F3/06 ,  G06F11/10

CPC classification number: G06F3/0652 ,  G06F3/0616 ,  G06F3/0659 ,  G06F3/0673 ,  G06F11/1076

Abstract: Methods, systems, and devices for scrub rate control for a memory device are described. For example, during a scrub operation, a memory device may perform an error correction operation on data read from a memory array of the memory device. The memory device may determine a quantity of errors detected or corrected during the scrub operation and determine a condition of the memory array based on the quantity of errors. The memory device may indicate the determined condition of the memory array to a host device. In some cases, the memory device may perform scrub operations based on one or more condition of the memory array. For example, as a condition of the memory array deteriorates, the memory device may perform scrub operations at an increased rate.

公开(公告)号：US20230122571A1

公开(公告)日：2023-04-20

申请号：US18082489

申请日：2022-12-15

Applicant: Micron Technology, Inc.

Inventor： Cheryl M. O'Donnell ,  Erica M. Gove ,  Zahra Hosseinimakarem ,  Debra M. Bell ,  Roya Baghi

IPC: G06F11/30 ,  G06F13/16 ,  G06F11/32

Abstract: Systems, apparatuses, and methods related to using memory device sensors are described. Some memory system or device types include sensors embedded in their circuitry. For instance, another device can be coupled to a memory device with an embedded sensor. The memory device can transmit a signal representing sensor data generated by the embedded sensor using a sensor output coupled to the other device. A controller coupled to a memory device may determine one or more threshold values of a sensor or sensors embedded in a memory device. The memory device may transmit an indication responsive to one or more sensors detecting a value greater or less than a threshold and may transmit the indication to another device.

公开(公告)号：US11586958B2

公开(公告)日：2023-02-21

申请号：US16840916

申请日：2020-04-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Di Wu ,  Anthony D. Veches ,  James S. Rehmeyer ,  Debra M. Bell ,  Libo Wang

IPC: G06N5/04 ,  G06N5/047 ,  G06K9/62 ,  G06N20/00

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, methods for performing operations associated with machine learning. Machine learning operations may include processing a data set, training a machine learning algorithm, and applying a trained algorithm to a data set. Some of the machine learning operations, such as pattern matching operations, may be performed within a memory device.

公开(公告)号：US11468938B2

公开(公告)日：2022-10-11

申请号：US17096469

申请日：2020-11-12

Applicant: Micron Technology, Inc.

Inventor： Vaughn N. Johnson ,  Debra M. Bell ,  Miles S. Wiscombe ,  Brian T. Pecha ,  Kyle Alexander

IPC: G11C11/406 ,  G11C11/408 ,  G11C11/4076

Abstract: Memory devices and systems with programmable refresh order and stagger times are disclosed herein. In one embodiment, a memory device includes a first memory bank group and a second memory bank group. The memory device is configured, in response to a refresh command, to perform a first refresh operation on the first memory bank group at a first time and a second refresh operation on the second memory bank group at a second time after the first time. The memory device is further configured to perform, in response to a read or write command, a read or write operation on the first memory bank group, the second memory bank group, or both the first and second memory bank groups after beginning the first refresh operation and before completing the second refresh operation.

公开(公告)号：US11435811B2

公开(公告)日：2022-09-06

申请号：US16707488

申请日：2019-12-09

Applicant: Micron Technology, Inc.

Inventor： Debra M. Bell ,  Roya Baghi ,  Erica M. Gove ,  Zahra Hosseinimakarem ,  Cheryl M. O'Donnell

IPC: G06F1/3234 ,  G11C16/26 ,  G11C11/56

Abstract: Systems, apparatuses, and methods related to using memory device sensors are described. Some memory system or device types include sensors embedded in their circuitry. For instance, a device can be coupled to a memory device with an embedded sensor. The memory device can transmit the data generated by the embedded sensor using a sensor output coupled to the device. The memory device may generate, based at least in part on a characteristic of a memory device, a signal from a sensor embedded in the memory device and transmit the signal generated by the sensor from the memory device to another device coupled to the memory device.

公开(公告)号：US11379124B2

公开(公告)日：2022-07-05

申请号：US17148326

申请日：2021-01-13

Applicant: Micron Technology, Inc.

Inventor： Debra M. Bell ,  Naveh Malihi

IPC: G06F3/06 ,  G11C7/06 ,  H03K19/20 ,  G06F21/79

Abstract: Apparatuses and methods related to updating data lines for data generation in, for example, a memory device or a computing system that includes a memory device. Updating data lines can include updating a plurality of data lines. The plurality of data lines can provide data form the memory array responsive to a receipt of the access command. The plurality of data lines can also be updated responsive to a determination that an access command received at a memory device is unauthorized.

公开(公告)号：US20220172768A1

公开(公告)日：2022-06-02

申请号：US17672537

申请日：2022-02-15

Applicant: Micron Technology, Inc.

Inventor： Gitanjali T. Ghosh ,  Debra M. Bell ,  Arunmozhi R. Subramaniam ,  Roya Baghi ,  Deepika Thumsi Umesh ,  Sue-Fern Ng

IPC: G11C11/408 ,  G11C11/4099 ,  G11C11/4076 ,  G11C11/4074

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to monitor degradations in word line characteristics. The memory device may generate a reference signal in response to an access command directed to a memory array including a plurality of word lines, in some embodiments. The memory array may include a victim word line configured to accumulate adverse effects of executing multiple access commands at the word lines of the memory array. When the degradation in the word line characteristics causes reliability issues (e.g., corrupted data), the memory array is deemed unreliable, and may be blocked from memory operations. The memory device may compare the reference signal and a signal from the victim word line to determine whether preventive measures may be appropriate to avoid (or mitigate) such reliability issues.

公开(公告)号：US20220148647A1

公开(公告)日：2022-05-12

申请号：US17096469

申请日：2020-11-12

Applicant: Micron Technology, Inc.

Inventor： Vaughn N. Johnson ,  Debra M. Bell ,  Miles S. Wiscombe ,  Brian T. Pecha ,  Kyle Alexander

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/408

Abstract: Memory devices and systems with programmable refresh order and stagger times are disclosed herein. In one embodiment, a memory device includes a first memory bank group and a second memory bank group. The memory device is configured, in response to a refresh command, to perform a first refresh operation on the first memory bank group at a first time and a second refresh operation on the second memory bank group at a second time after the first time. The memory device is further configured to perform, in response to a read or write command, a read or write operation on the first memory bank group, the second memory bank group, or both the first and second memory bank groups after beginning the first refresh operation and before completing the second refresh operation.

公开(公告)号：US20220107905A1

公开(公告)日：2022-04-07

申请号：US17062484

申请日：2020-10-02

Applicant: Micron Technology, Inc.

Inventor： Debra M. Bell ,  Vaughn N. Johnson ,  Kyle Alexander ,  Gary L. Howe ,  Brian T. Pecha ,  Miles S. Wiscombe

IPC: G06F13/16 ,  G11C11/4096 ,  G11C11/406

Abstract: Memory devices and systems with improved command/address bus utilization are disclosed herein. In one embodiment, a memory device comprises a plurality of external command/address terminals and a command decoder. The plurality of external command/address terminals are configured to receive a command as a corresponding plurality of command/address bits. A first set of the command/address bits indicate a read or write operation. A second set of the command/address bits indicate whether to execute a refresh operation. The memory device is configured to, in response to the first set of command/address bits, execute the read or write operation on a portion of a memory array. The memory device is further configured to, in response to the second set of command/address bits, execute the refresh operation to refresh at least one memory bank of the memory array when the second set of command/address bits indicate that the refresh operation should be executed.