公开(公告)号：US20240047450A1

公开(公告)日：2024-02-08

申请号：US18491694

申请日：2023-10-20

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Kunal R. Parekh

IPC: H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H10B12/00

CPC classification number: H01L25/18 ,  H01L25/50 ,  H01L24/83 ,  H10B12/33 ,  H10B12/036 ,  H10B12/482 ,  H10B12/485 ,  H10B12/488 ,  H01L2224/83895 ,  H01L2224/83896

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure assembly comprising memory cells, digit lines coupled to the memory cells, word lines coupled to the memory cells, and isolation material overlying the memory cells, the digit lines, and the word lines. An additional microelectronic device structure assembly comprising control logic devices and additional isolation material overlying the control logic devices is formed. The additional isolation material of the additional microelectronic device structure assembly is bonded to the isolation material of the microelectronic device structure assembly to attach the additional microelectronic device structure assembly to the microelectronic device structure assembly. The memory cells are electrically connected to at least some of the control logic devices after bonding the additional isolation material to the isolation material. Microelectronic devices, electronic systems, and additional methods are also described.

公开(公告)号：US11862569B2

公开(公告)日：2024-01-02

申请号：US17325069

申请日：2021-05-19

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh

IPC: H01L23/538 ,  H01L21/50 ,  H01L21/768 ,  H01L27/06 ,  H01L27/092

CPC classification number: H01L23/5384 ,  H01L21/50 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5386 ,  H01L27/0688 ,  H01L27/092

Abstract: Systems and methods for a semiconductor device having a front-end-of-line interconnect structure are provided. The semiconductor device may include a dielectric material having a backside formed on a front side of a semiconductor or silicon substrate material and a front side, and a conducting material on the front side of the dielectric material. The conducting material may have a line portion and an interconnect structure electrically coupled to the line portion and separated from the front side of the substrate material by the dielectric material. The interconnect structure has a backside defining a contact surface. The semiconductor device may further include a semiconductor die proximate the front side of the dielectric material, an insulating material encasing at least a portion of the semiconductor die, and an opening through which the active contact surface at the backside of the interconnect structure is exposed for electrical connection.

公开(公告)号：US11837594B2

公开(公告)日：2023-12-05

申请号：US17364476

申请日：2021-06-30

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Kunal R. Parekh

IPC: H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H10B12/00

CPC classification number: H01L25/18 ,  H01L24/83 ,  H01L25/50 ,  H10B12/036 ,  H10B12/33 ,  H10B12/482 ,  H10B12/485 ,  H10B12/488 ,  H01L2224/83895 ,  H01L2224/83896

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure assembly comprising memory cells, digit lines coupled to the memory cells, contact structures coupled to the digit lines, word lines coupled to the memory cells, additional contact structures coupled to the word lines, and isolation material surrounding the contact structures and the additional contact structures and overlying the memory cells. An additional microelectronic device structure assembly is formed and comprises control logic devices, further contact structures coupled to the control logic devices, and additional isolation material surrounding the further contact structures and overlying the control logic devices. The additional microelectronic device structure assembly is attached to the microelectronic device structure assembly by bonding the additional isolation material to the isolation material and by bonding the further contact structures to the contact structures and the additional contact structures. Microelectronic devices and electronic systems are also described.

公开(公告)号：US20230282627A1

公开(公告)日：2023-09-07

申请号：US18111266

申请日：2023-02-17

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  Hernan A. Castro

IPC: H01L25/16 ,  H01L23/00 ,  H10B80/00 ,  H01L21/66 ,  G06N3/063 ,  H01L21/324 ,  H01L21/3105 ,  H01L21/321

CPC classification number: H01L25/16 ,  G06N3/063 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/324 ,  H01L22/32 ,  H01L24/08 ,  H01L24/16 ,  H01L24/48 ,  H01L24/80 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2924/1011 ,  H01L2924/1431 ,  H01L2924/1438

Abstract: Semiconductor memory dies bonded to logic dies and associated systems and methods are disclosed. In an embodiment, a semiconductor die assembly includes a logic die and one or more memory dies directly bonded to the logic die. The logic die includes integrated circuits generated using relatively high temperature process steps whereas the memory dies include memory cells with materials generated using relatively low temperature process steps. The logic die and the memory dies have been separately fabricated in two different wafers such that process steps generating them can be optimized independently of each other. The resulting semiconductor device including the memory dies bonded to the logic die functions as a single device as if they were formed in a monolithic substrate. The resulting semiconductor device may be configured to perform artificial intelligence tasks.

公开(公告)号：US20230268351A1

公开(公告)日：2023-08-24

申请号：US18096458

申请日：2023-01-12

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  James B. Johnson

IPC: H01L27/12

CPC classification number: H01L27/124

Abstract: A semiconductor device assembly includes a first semiconductor device having a first plurality of electrical contacts with a first average pitch, a second semiconductor device over the first semiconductor device and having a second plurality of electrical contacts with a second average pitch, and a signal routing structure between the first and second semiconductor devices and including a first plurality of conductive structures, each in contact with one of the first plurality of electrical contacts, a second plurality of conductive structures, each in contact with one of the second plurality of electrical contacts, and a pattern of parallel conductive lines between the first and second pluralities of conductive structures. The pattern of parallel conductive lines has a third average pitch less than the first and second average pitches, and pairs of conductive structures from the first and second pluralities are electrically coupled by different ones of the parallel conductive lines.

公开(公告)号：US20230260964A1

公开(公告)日：2023-08-17

申请号：US17711583

申请日：2022-04-01

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Kyle K. Kirby ,  Bret K. Street ,  Kunal R. Parekh

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06589

Abstract: A semiconductor device having monolithic conductive cylinders, and associated systems and methods, are disclosed herein. The semiconductor device can include a semiconductor substrate, a conductive pad, an opening, and a top dielectric layer. The conductive pad may be at a first surface of the semiconductor substrate. The opening may be ring-shaped and extend through the semiconductor substrate from the conductive pad to a second surface and define a side wall. The liner may coat the side wall and the top dielectric layer may cover the second surface and may fill the opening. A second ring-shaped opening may be formed through the semiconductor device and the opening and a conductive material plated therein.

公开(公告)号：US20230260875A1

公开(公告)日：2023-08-17

申请号：US17670378

申请日：2022-02-11

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Kyle K. Kirby ,  Bret K. Street ,  Kunal R. Parekh

IPC: H01L23/48 ,  H01L21/768 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L21/76877 ,  H01L25/0657 ,  H01L24/08 ,  H01L24/32 ,  H01L24/83 ,  H01L2225/06541 ,  H01L2224/08146 ,  H01L2224/32145 ,  H01L2224/8319

Abstract: A semiconductor device having monolithic conductive columns, and associated systems and methods, are disclosed herein. The semiconductor device can include a semiconductor substrate, a conductive pad, an opening, a non-conductive liner, and a plug of non-conductive material. The conductive pad may be at a surface of the semiconductor substrate. The opening may extend through the semiconductor substrate from the conductive pad to a second surface and define a side wall. The liner may coat the side wall and the plug may fill the opening. A second opening may be formed through the semiconductor device and the opening and a conductive material plated therein.

公开(公告)号：US11699652B2

公开(公告)日：2023-07-11

申请号：US16905698

申请日：2020-06-18

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh

IPC: H01L29/00 ,  H01L23/522 ,  G11C7/18 ,  H01L23/00 ,  H01L23/528 ,  H01L25/18 ,  H10B41/27 ,  H10B41/35

CPC classification number: H01L23/5226 ,  G11C7/18 ,  H01L23/5283 ,  H01L24/05 ,  H01L25/18 ,  H10B41/27 ,  H10B41/35 ,  H01L2924/1431 ,  H01L2924/1443

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure, a doped semiconductive material overlying the base structure, a stack structure overlying the doped semiconductive material, cell pillar structures vertically extending through the stack structure and the doped semiconductive material and into the base structure, and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The base structure and portions of the cell pillar structures vertically extending into the base structure are removed to expose the doped semiconductive material. The doped semiconductive material is then patterned to form at least one source structure over the stack structure and coupled to the cell pillar structures. Microelectronic devices and electronic systems are also described.

公开(公告)号：US11696443B2

公开(公告)日：2023-07-04

申请号：US17383988

申请日：2021-07-23

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh

IPC: H10B43/27 ,  H01L29/06 ,  H01L21/02 ,  H10B41/27 ,  H01L21/768 ,  H01L21/762

CPC classification number: H10B43/27 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/76224 ,  H01L21/76877 ,  H01L29/0649 ,  H10B41/27

Abstract: Some embodiments include an integrated assembly having a conductive structure which includes a semiconductor material over a metal-containing material. A stack of alternating conductive levels and insulative levels is over the conductive structure. A partition extends through the stack. The partition has wall regions, and has corner regions where two or more wall regions meet. The conductive structure includes a first portion which extends directly under the corner regions, and includes a second portion which is directly under the wall regions and is not directly under the corner regions. The first portion has a first thickness of the semiconductor material and the second portion has a second thickness of the semiconductor material. The first thickness is greater than the second thickness. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20230139175A1

公开(公告)日：2023-05-04

申请号：US17719241

申请日：2022-04-12

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/48 ,  H01L25/00

Abstract: A semiconductor device assembly includes a first semiconductor device including a plurality of electrical contacts on an upper surface thereof, a monolithic silicon structure having a lower surface in contact with the upper surface and a cavity extending from the lower surface into a body of the monolithic silicon structure; a second semiconductor device disposed in the cavity, the second semiconductor device including a first plurality of interconnects, each operatively coupled to a corresponding one of the plurality of electrical contacts, and a second plurality of interconnects on an upper surface of the second semiconductor device, each coupled to a corresponding TSV of a plurality of TSVs extending from the cavity to a top surface of the monolithic silicon structure; and a third semiconductor device disposed over the monolithic silicon structure and including a third plurality of interconnects, each operatively coupled to a corresponding one of the plurality of TSVs.