公开(公告)号：US20150199287A1

公开(公告)日：2015-07-16

申请号：US14595030

申请日：2015-01-12

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: G06F13/24 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F13/24 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/4295

Abstract: Master and slave devices may be coupled to a control data bus. A method includes controlling data transmissions over a bus from a master device, where data bits are transcoded into symbols for transmission across two lines of the bus and a clock signal is embedded within symbol transitions of the data transmissions, and providing an interrupt period, during which one or more slave devices coupled to the bus can assert an interrupt request on a first line of the bus, within part of a heartbeat transmission by the master device over the first line and a second tine of the bus. The interrupt request may be an indicator that the asserting slave device wishes to request some action by the master device.

Abstract translation: 主设备和从设备可以耦合到控制数据总线。 一种方法包括控制来自主设备的总线上的数据传输，其中数据位被转码为用于在总线的两条线路上传输的符号，并且时钟信号嵌入在数据传输的符号转换内，并在提供中断周期期间提供中断周期 耦合到总线的一个或多个从设备可以在主设备通过第一线路的心跳传输的一部分内部和总线的第二齿之上，在总线的第一行上断言中断请求。 中断请求可以是断言从设备希望请求主设备的一些动作的指示符。

公开(公告)号：US20150100862A1

公开(公告)日：2015-04-09

申请号：US14511160

申请日：2014-10-09

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: G06F11/10 ,  G06F13/42

CPC classification number: G06F11/1004 ,  G06F13/4221 ,  H03M13/096

Abstract: A device is provided comprising a shared bus, a slave device, and a master device. The slave device may be coupled to the shared bus. The master device may be coupled to the control data bus and adapted to manage communications on the shared bus. Transmissions over the shared bus are a plurality of bits that are encoded into ternary numbers which are then transcoded into symbols for transmission, and either the 3 least significant bits or the least significant in the plurality of bits are used for error detection of the transmission.

Abstract translation: 提供了包括共享总线，从设备和主设备的设备。 从设备可以耦合到共享总线。 主设备可以耦合到控制数据总线并且适于管理共享总线上的通信。 通过共享总线的传输是被编码成三进制数的多个比特，然后被转码成用于传输的符号，并且多个比特中的3个最低有效比特或最低有效位用于该传输的错误检测。

公开(公告)号：US20150100713A1

公开(公告)日：2015-04-09

申请号：US14510069

申请日：2014-10-08

Applicant: QUALCOMM INCORPORATED

Inventor： Shoichiro Sengoku

IPC: G06F13/42 ,  G06F13/24 ,  G06F13/364

CPC classification number: G06F13/4291 ,  G06F13/24 ,  G06F13/364 ,  Y02D10/14 ,  Y02D10/151

Abstract: A plurality of slave devices is coupled to a control data bus along with at least one master device that is managing access of slave devices to the control data bus. At least one slave device operates in a sI2C protocol mode of operation and at least one other slave device operates in a CCIe mode of operation. At least the slave devices using sI2C protocol mode use the control data bus for interrupt requests. In order to maintain the integrity of CCIe communications, the slave devices using the sI2C protocol mode disables issuing IRQs when the control data bus operates according to the CCIe mode.

Abstract translation: 多个从设备连同至少一个正在管理从设备对控制数据总线的访问的主设备耦合到控制数据总线。 至少一个从设备以sI2C协议操作模式操作，并且至少一个其他从设备以CCIe操作模式操作。 至少使用sI2C协议模式的从设备将控制数据总线用于中断请求。 为了保持CCIe通信的完整性，当控制数据总线根据CCIe模式运行时，使用sI2C协议模式的从设备禁止发出IRQ。

公开(公告)号：US20150074305A1

公开(公告)日：2015-03-12

申请号：US14480540

申请日：2014-09-08

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku ,  Richard Dominic Wietfeldt ,  George Alan Wiley

IPC: G06F13/362 ,  G06F11/30 ,  G06F13/24

CPC classification number: G06F13/378 ,  G06F13/24 ,  G06F13/36 ,  G06F13/362 ,  G06F2213/3602

Abstract: To accommodate multiple masters over bus architectures supporting a single master device, a mechanism is provided for an inactive master device to trigger an IRQ signal over a shared, single line IRQ bus. A current master then polls the other inactive master devices over a shared data bus to ascertain which inactive master device is asserting the IRQ signal. Upon identifying the asserting inactive master device, the current master device grants control of the data bus to the new master device, thereby making the inactive master the new active master device.

Abstract translation: 为了通过支持单个主器件的总线架构来容纳多个主器件，提供了一种用于非活动主器件以通过共享的单线IRQ总线触发IRQ信号的机制。 然后当前主机通过共享数据总线轮询其他无效主设备，以确定哪个无效主设备正在断言IRQ信号。 当识别出断言无效的主设备时，当前的主设备将数据总线的控制权授予新的主设备，从而使非活动主设备成为新的主主设备。

公开(公告)号：US20150058507A1

公开(公告)日：2015-02-26

申请号：US14462363

申请日：2014-08-18

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku ,  Richard Dominic Wietfeldt ,  George Alan Wiley

IPC: G06F13/42 ,  G06F13/24

CPC classification number: G06F13/4226 ,  G06F13/22 ,  G06F13/24 ,  G06F13/26 ,  G06F2211/001 ,  G06F2211/002

Abstract: A master device is provided which is coupled to a shared single line interrupt request (IRQ) bus and a control data bus. The master device group slave devices coupled to the shared single line IRQ bus into one or more groups, where each group is associated with a different IRQ signal. The master device then monitors the IRQ bus to ascertain when an IRQ signal is asserted by at least one slave device. The master device then identifies a group to with which the IRQ signal is associated. The slave devices for the identified group are then scanned or queried by the master device to ascertain which slave device asserted the IRQ signal on the IRQ bus. Each group uses a distinguishable IRQ signal to allow the master device to ascertain which group to query or scan.

Abstract translation: 提供了一个主器件，其耦合到共享单线中断请求（IRQ）总线和控制数据总线。 主设备组从设备将共享单线IRQ总线耦合到一个或多个组中，其中每个组与不同的IRQ信号相关联。 然后，主设备监视IRQ总线以确定至少一个从设备何时确定IRQ信号。 然后，主设备识别与IRQ信号相关联的组。 然后由主设备扫描或查询所识别的组的从设备，以确定哪个从设备在IRQ总线上断言IRQ信号。 每个组使用可区分的IRQ信号来允许主设备确定哪个组进行查询或扫描。

公开(公告)号：US20140372643A1

公开(公告)日：2014-12-18

申请号：US14302362

申请日：2014-06-11

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku ,  George Alan Wiley ,  Joseph Cheung

IPC: G06F13/42

CPC classification number: G06F13/4291 ,  G06F13/364 ,  G06F13/4282 ,  G06F13/4295 ,  H04L7/0331

Abstract: System, methods and apparatus are described that offer improved performance of a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. CCI extension (CCIe) devices are described. CCIe devices may be configured as a bus master or as a slave. In one method, a CCIe transmitter may generate a transition number from a set of bits, convert the transition number into a sequence of symbols, and transmit the sequence of symbols in the signaling state of a two-wire serial bus. Timing information may be encoded in the transitions between symbols of consecutive pairs of symbols in the sequence of symbols. For example, each transition may cause a change in the signaling state of at least one wire of the two-wire serial bus. A CCIe receiver may derive a receive clock from the transitions in order to receive and decode the sequence of symbols.

Abstract translation: 描述了提供用于内部集成电路（I2C）和/或相机控制接口（CCI）操作的串行总线的改进的性能的系统，方法和装置。 描述CCI扩展（CCIe）设备。 CCIe设备可以配置为总线主机或从机。 在一种方法中，CCIe发射机可以从一组比特生成转换号码，将转换号码转换为符号序列，并以两线串行总线的信令状态发送符号序列。 定时信息可以在符号序列中的连续符号对符号之间的转换中被编码。 例如，每个转换可能导致两线串行总线的至少一根线的信令状态改变。 CCIe接收机可以从转换中导出接收时钟，以便接收和解码符号序列。

公开(公告)号：US20140254733A1

公开(公告)日：2014-09-11

申请号：US14199322

申请日：2014-03-06

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku ,  Chulkyu Lee ,  George Alan Wiley ,  Joseph Cheung

IPC: H04L7/027

CPC classification number: H04L7/033 ,  H03K5/1252 ,  H03K5/1534 ,  H04L7/0066 ,  H04L7/027 ,  H04L25/0272 ,  H04L25/14 ,  H04L25/49 ,  H04L25/4906 ,  H04L25/493

Abstract: A clock recovery circuit is provided comprising a receiver circuit and a clock extraction circuit. The receiver circuit may be adapted to decode a differentially encoded signal on a plurality of data lines, where at least one data symbol is differentially encoded in state transitions of the differentially encoded signal. The clock extraction circuit may be adapted to obtain a clock signal from state transition signals derived from the state transitions while compensating for skew in the different data lines, and masking data state transition glitches.

Abstract translation: 提供了一种包括接收机电路和时钟提取电路的时钟恢复电路。 接收器电路可以适于对多条数据线上的差分编码信号进行解码，其中至少一个数据符号在差分编码信号的状态转换中进行差分编码。 时钟提取电路可以适于从补偿状态转变的状态转变信号获得时钟信号，同时补偿不同数据线中的偏斜，并且屏蔽数据状态转换毛刺。

公开(公告)号：US20140254711A1

公开(公告)日：2014-09-11

申请号：US13832990

申请日：2013-03-15

Applicant: QUALCOMM INCORPORATED

Inventor： Shoichiro Sengoku ,  George Alan Wiley ,  Chulkyu Lee ,  Joseph Cheung

IPC: H03H2/00 ,  H04B1/04

CPC classification number: H03H2/005 ,  H04B1/04 ,  H04L25/0272 ,  H04L25/0278 ,  H04L25/14 ,  Y02D30/30

Abstract: A termination network circuit for a differential signal transmitter comprises a plurality of n resistance elements and a plurality of differential signal drivers. A first end of each of the resistance elements is coupled at a common node, where n is an integer value and is the number of conductors used to transmit a plurality of differential signals. Each differential signal driver may include a positive terminal driver and a negative terminal driver. The positive terminal driver is coupled to a second end of a first resistance element while the negative terminal driver is coupled to a second end of a second resistance element. The positive terminal driver and the negative terminal driver are separately and independently switchable to provide a current having a magnitude and direction. During a transmission cycle each of the resistance elements has a current of a different magnitude and/or direction than the other resistance elements.

Abstract translation: 用于差分信号发射机的终端网络电路包括多个n个电阻元件和多个差分信号驱动器。 每个电阻元件的第一端在公共节点处耦合，其中n是整数值，并且是用于发送多个差分信号的导体的数量。 每个差分信号驱动器可以包括正极端子驱动器和负极端子驱动器。 正端子驱动器耦合到第一电阻元件的第二端，而负端子驱动器耦合到第二电阻元件的第二端。 正极端子驱动器和负极端子驱动器分别独立地切换以提供具有幅度和方向的电流。 在传输周期期间，每个电阻元件具有与其它电阻元件不同的幅度和/或方向的电流。