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179 条记录 (耗时 0.041 秒)

    Layer arrangement and process for producing a layer arrangement
    102.
    发明申请
    Layer arrangement and process for producing a layer arrangement 审中-公开
    用于生产层布置的层布置和工艺

    公开(公告)号：US20060035442A1

    公开(公告)日：2006-02-16

    申请号：US11175912

    申请日：2005-07-05

    申请人： Gurkan Ilicali ,  Erhard Landgraf ,  Wolfgang Roesner ,  Franz Hofmann

    发明人： Gurkan Ilicali ,  Erhard Landgraf ,  Wolfgang Roesner ,  Franz Hofmann

    IPC分类号： H01L21/30

    CPC分类号： H01L29/66772 ,  H01L29/66628 ,  H01L29/78648 ,  H01L29/78654

    摘要： In a process for producing a layer arrangement, a first layer is formed with a thickness on a first side of a substrate, which thickness is greater than a minimum thickness for epitaxial growth, a second layer is epitaxially grown on the first layer, and a third layer is formed on the second layer. Furthermore, a handling wafer is bonded to the third layer, the substrate is removed from a second side, which is the opposite side to the first side of the substrate, and the first layer is thinned in subregions from the second side, so that after the thinning the thickness of the first layer is lower than a minimum thickness for epitaxial growth.

    摘要翻译： 在制造层布置的方法中，第一层在衬底的第一侧上形成厚度，该厚度大于用于外延生长的最小厚度，第二层在第一层上外延生长，并且 第三层形成在第二层上。 此外，将处理晶片接合到第三层，从与衬底的第一侧相反的一侧的第二侧除去衬底，并且第二层在第二侧的次级区域中变薄，使得在 使第一层的厚度变薄比外延生长的最小厚度低。

    Fabrication method for memory cell
    103.
    发明授权
    Fabrication method for memory cell 失效
    存储单元制造方法

    公开(公告)号：US06982202B2

    公开(公告)日：2006-01-03

    申请号：US10899436

    申请日：2004-07-26

    申请人： Franz Hofmann ,  Erhard Landgraf ,  Hannes Luyken

    发明人： Franz Hofmann ,  Erhard Landgraf ,  Hannes Luyken

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792

    摘要： Method of fabricating a memory cell, in which a storage layer, which is designed for programming by charge carrier trapping, and a gate electrode, which is electrically insulated from a semiconductor material, are fabricated at a top side of a semiconductor body or a semiconductor layer structure above a channel region provided between doped source-drain regions. The method includes the steps of fabricating at least one trench in the top side, providing at least portions of the trench walls which adjoin the source-drain regions to be fabricated with the storage layer, depositing a material provided for the gate electrode into the trench, forming the source-drain regions by covering the gate electrode, removing, on both sides of the trench, the semiconductor material down to an intended depth, and implanting dopant, and applying an insulation layer to the source-drain region, and fabricating an electrical connection for the gate electrode.

    摘要翻译： 制造存储单元的方法，其中设计用于通过电荷载流子捕获进行编程的存储层和与半导体材料电绝缘的栅电极制造在半导体本体或半导体的顶侧 在设置在掺杂源极 - 漏极区之间的沟道区域之上的层结构。 该方法包括以下步骤：在顶侧制造至少一个沟槽，提供沟槽壁的至少部分，其邻接待制造的源极 - 漏极区域与存储层，将为栅电极提供的材料沉积到沟槽 通过覆盖栅极电极形成源极 - 漏极区域，在沟槽的两侧将半导体材料去除到预期深度，并且注入掺杂剂，并且向源极 - 漏极区域施加绝缘层，并且制造 栅电极的电连接。

    Memory element and method for fabricating a memory element
    104.
    发明授权
    Memory element and method for fabricating a memory element 失效
    用于制造存储元件的存储元件和方法

    公开(公告)号：US06730930B2

    公开(公告)日：2004-05-04

    申请号：US10275598

    申请日：2003-04-21

    申请人： Franz Hofmann ,  Richard Johannes Luyken ,  Wolfgang Rösner

    发明人： Franz Hofmann ,  Richard Johannes Luyken ,  Wolfgang Rösner

    IPC分类号： H01L3524

    CPC分类号： H01L27/28 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0016 ,  G11C2213/77 ,  H01L51/0575

    摘要： A memory element with organic material comprises two metallized layers, arranged one on top of the other, with first lines and second lines which are arranged to intersect with each other. A channel is formed at the intersections between the first line and the second line, which overlaps the first line partially and completely overlaps the second line. The channels are filled with a filling material, the electrical conductivity of which may be altered by an applied electrical voltage.

    摘要翻译： 具有有机材料的存储元件包括两个金属化层，其一个在另一个的顶部上，第一线和第二线被布置为彼此相交。 在第一线和第二线之间的交叉处形成通道，其与第一线重叠，并且与第二线完全重叠。 通道填充有填充材料，其电导率可以通过施加的电压而改变。

    Substrate assembly having a depression suitable for an integrated circuit configuration and method for its fabrication
    106.
    发明授权
    Substrate assembly having a depression suitable for an integrated circuit configuration and method for its fabrication 有权
    具有适于集成电路结构的凹陷的衬底组件及其制造方法

    公开(公告)号：US06608340B1

    公开(公告)日：2003-08-19

    申请号：US09821853

    申请日：2001-03-30

    申请人： Franz Hofmann ,  Till Schlösser ,  Josef Willer

    发明人： Franz Hofmann ,  Till Schlösser ,  Josef Willer

    IPC分类号： H01L2972

    CPC分类号： H01L27/10864

    摘要： A depression extends from a main surface of the substrate to the inside of said substrate and has an upper area and an adjacent lower area. A cross-section of the upper area, parallel to the main surface, is provided with at least one corner. A cross-section of the lower area, parallel to the main surface, matches the cross-section of the upper area, particularly in the vicinity the upper area, with the following difference: each corner is rounded, whereby the cross section of the lower area is smaller than the cross-section of the upper area. In order to produce the indentation, the upper area is provided with an auxiliary spacer that is rounded by isotropic etching. The lower area is produced by selectively etching the substrate to form an auxiliary spacer.

    摘要翻译： 凹陷从基板的主表面延伸到所述基板的内部，并且具有上部区域和相邻的下部区域。 平行于主表面的上部区域的横截面设置有至少一个角部。 平行于主表面的下部区域的横截面与上部区域的横截面特别是在上部区域附近匹配，具有以下差异：每个角都是圆形的，由此下部区域的横截面 面积小于上部区域的横截面。 为了产生凹陷，上部区域设置有通过各向同性蚀刻而被圆化的辅助间隔件。 通过选择性地蚀刻基板以形成辅助间隔物来产生下部区域。

    SOI DRAM without floating body effect
    107.
    发明授权
    SOI DRAM without floating body effect 有权
    SOI DRAM无浮体效应

    公开(公告)号：US06599797B1

    公开(公告)日：2003-07-29

    申请号：US09980811

    申请日：2002-03-11

    申请人： Franz Hofmann ,  Josef Willer

    发明人： Franz Hofmann ,  Josef Willer

    IPC分类号： H01L218242

    CPC分类号： H01L27/10873 ,  H01L27/10888 ,  H01L27/1203

    摘要： The invention relates to an SOI substrate which is provided with a recess that cuts through the silicon layer and the SiO2 layer (O). An upper part of said recess (V) which is located in the range of the silicon layer (S) has cylindrical shape with a horizontal first cross-section. A lower part of the recess (V) which is located in the range of the SiO2 layer (O), compared with the upper part of the recess (V), is bulged to such an extent that it has a cylindrical shape with a horizontal second cross-section that is larger than the first cross-section. A cylinder (Z) of an insulating material is provided in the recess (V). The horizontal cross-section of said cylinder corresponds to the first cross-section and the lower part thereof is located in the lower part of the recess (V). The dent laterally surrounds the lower part of the cylinder (Z). A conducting structure (L) is located in the dent and adjoins the silicon layer (S) and the silicon substrate (1) so that the channel zone of the MOS transistors is electrically connected to the silicon substrate.

    摘要翻译： 本发明涉及一种SOI衬底，其具有穿过硅层和SiO 2层（O）的凹部。 位于硅层（S）的范围内的所述凹部（V）的上部具有水平的第一横截面的圆筒形状。 与凹部（V）的上部相比，位于SiO 2层（O）的范围内的凹部（V）的下部被凸出到具有水平的圆筒形状的程度 第二横截面大于第一横截面。 在凹部（V）中设置绝缘材料的圆筒（Z）。 所述气缸的水平截面对应于第一横截面，其下部位于凹部（V）的下部。 凹陷横向围绕气缸（Z）的下部。 导电结构（L）位于凹陷中并与硅层（S）和硅衬底（1）相邻，使得MOS晶体管的沟道区电连接到硅衬底。

    Integrated circuit configuration having at least one transistor and one capacitor, and method for fabricating it
    108.
    发明授权
    Integrated circuit configuration having at least one transistor and one capacitor, and method for fabricating it 有权
    具有至少一个晶体管和一个电容器的集成电路配置及其制造方法

    公开(公告)号：US06593614B1

    公开(公告)日：2003-07-15

    申请号：US09716336

    申请日：2000-11-20

    申请人： Franz Hofmann ,  Wolfgang Krautschneider

    发明人： Franz Hofmann ,  Wolfgang Krautschneider

    IPC分类号： H01L27108

    CPC分类号： H01L27/10852 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/10876

    摘要： A patterned conductive layer and a structure via which a transistor can be driven, e.g. a word line, are disposed one above the other. A vertical conductive structure, e.g. a spacer, connects a first source/drain region of the transistor to the conductive layer, with which it forms a first capacitor electrode which has a large effective area in conjunction with a high packing density. A capacitor dielectric is disposed over the vertical conductive structure and the conductive layer, and a second capacitor electrode is disposed over the capacitor dielectric. The vertical conductive structure may be disposed on a first sidewall of the first source/drain region and a gate electrode of the transistor may be disposed on an adjoining second sidewall of the first source/drain region. The circuit configuration may form a DRAM cell configuration.

    摘要翻译： 图案化的导电层和可以驱动晶体管的结构，例如， 一个字线，一个在另一个之上。 垂直导电结构，例如 间隔件将晶体管的第一源极/漏极区域连接到导电层，由此形成第一电容器电极，其具有大的有效面积并结合高的堆积密度。 电容器电介质设置在垂直导电结构和导电层之上，并且第二电容器电极设置在电容器电介质上。 垂直导电结构可以设置在第一源极/漏极区域的第一侧壁上，并且晶体管的栅电极可以设置在第一源极/漏极区域的相邻的第二侧壁上。 电路配置可以形成DRAM单元配置。

    Integrated CMOS circuit configuration, and production of same
    109.
    发明授权
    Integrated CMOS circuit configuration, and production of same 有权
    集成CMOS电路配置，生产相同

    公开(公告)号：US06518628B1

    公开(公告)日：2003-02-11

    申请号：US09423864

    申请日：1999-11-15

    申请人： Wolfgang Krautschneider ,  Franz Hofmann ,  Lothar Risch

    发明人： Wolfgang Krautschneider ,  Franz Hofmann ,  Lothar Risch

    IPC分类号： H01L2976

    CPC分类号： H01L27/0922

    摘要： An integrated CMOS circuit arrangement and a method of manufacturing same, which includes both a first MOS transistor and a second MOS transistor complementary thereto, wherein one of the MOS transistors is arranged at the floor of a trench and the other is arranged at the principal surface of a semiconductor substrate. The MOS transistors are arranged relative to one another such that a current flow through the MOS transistors respectively occurs substantially parallel to a sidewall of the trench that is arranged between the MOS transistors.

    摘要翻译： 一种集成CMOS电路装置及其制造方法，其包括第一MOS晶体管和与其互补的第二MOS晶体管，其中MOS晶体管中的一个布置在沟槽的底部，而另一个布置在主表面 的半导体衬底。 MOS晶体管相对于彼此布置，使得流过MOS晶体管的电流分别基本上平行于布置在MOS晶体管之间的沟槽的侧壁。

    Method of forming DRAM cell arrangement
    110.
    发明授权
    Method of forming DRAM cell arrangement 有权
    形成DRAM单元布置的方法

    公开(公告)号：US06352894B1

    公开(公告)日：2002-03-05

    申请号：US09482064

    申请日：2000-01-13

    申请人： Bernd Goebel ,  Wolfgang Roesner ,  Franz Hofmann ,  Emmerich Bertagnolli ,  Eve Marie Martin

    发明人： Bernd Goebel ,  Wolfgang Roesner ,  Franz Hofmann ,  Emmerich Bertagnolli ,  Eve Marie Martin

    IPC分类号： H01L218242

    CPC分类号： H01L27/10876 ,  H01L27/10808 ,  H01L27/10823 ,  Y10S257/906 ,  Y10S438/947

    摘要： A storage cell has a number of projections of a semiconductor substrate arranged in rows and columns, neighboring rows of the projections being translation-symmetrical in relation to a y-axis which extends parallel to the columns. Each of the projections has at least one first source/drain region of a selection transistor and one channel region arranged below the first source/drain region, which is surrounded by a gate electrode annularly. A storage capacitor is connected between the first source/drain region and a bit line. The bit line as well as the storage capacitor are arranged essentially above the semiconductor substrate. Second source/drain regions of selection transistors are buried in the semiconductor substrate and connected with each other. Word lines can be formed self-justified in the form of adjacent gate electrodes. The projections can be created by etching with only one mask. The storage cell can be produced with an area of 4F2, F being the minimal structural size that can be produced in the respective technology.

    摘要翻译： 存储单元具有排列成行和列的半导体衬底的多个突起，相邻的一列突起相对于平行于列延伸的y轴平移对称。 每个突起具有选择晶体管的至少一个第一源极/漏极区域和布置在第一源极/漏极区域下方的一个沟道区域，其被环形的栅极电极包围。 存储电容器连接在第一源极/漏极区域和位线之间。 位线以及存储电容器基本上布置在半导体衬底的上方。 选择晶体管的第二源极/漏极区域被埋在半导体衬底中并彼此连接。 字线可以形成为相邻栅电极的形式自对称。 可以通过仅使用一个掩模的蚀刻来产生突起。 可以生产具有4F2面积的存储单元，F是可以在各自技术中生产的最小结构尺寸。