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    Layer arrangement and process for producing a layer arrangement
    1.
    发明申请
    Layer arrangement and process for producing a layer arrangement 审中-公开
    用于生产层布置的层布置和工艺

    公开(公告)号：US20060035442A1

    公开(公告)日：2006-02-16

    申请号：US11175912

    申请日：2005-07-05

    申请人： Gurkan Ilicali ,  Erhard Landgraf ,  Wolfgang Roesner ,  Franz Hofmann

    发明人： Gurkan Ilicali ,  Erhard Landgraf ,  Wolfgang Roesner ,  Franz Hofmann

    IPC分类号： H01L21/30

    CPC分类号： H01L29/66772 ,  H01L29/66628 ,  H01L29/78648 ,  H01L29/78654

    摘要： In a process for producing a layer arrangement, a first layer is formed with a thickness on a first side of a substrate, which thickness is greater than a minimum thickness for epitaxial growth, a second layer is epitaxially grown on the first layer, and a third layer is formed on the second layer. Furthermore, a handling wafer is bonded to the third layer, the substrate is removed from a second side, which is the opposite side to the first side of the substrate, and the first layer is thinned in subregions from the second side, so that after the thinning the thickness of the first layer is lower than a minimum thickness for epitaxial growth.

    摘要翻译： 在制造层布置的方法中，第一层在衬底的第一侧上形成厚度，该厚度大于用于外延生长的最小厚度，第二层在第一层上外延生长，并且 第三层形成在第二层上。 此外，将处理晶片接合到第三层，从与衬底的第一侧相反的一侧的第二侧除去衬底，并且第二层在第二侧的次级区域中变薄，使得在 使第一层的厚度变薄比外延生长的最小厚度低。

    Integrated circuit array
    2.
    发明申请
    Integrated circuit array 审中-公开
    集成电路阵列

    公开(公告)号：US20050224888A1

    公开(公告)日：2005-10-13

    申请号：US11116139

    申请日：2005-04-27

    申请人： Andrew Graham ,  Franz Hofmann ,  Wolfgang Honlein ,  Johannes Kretz ,  Franz Kreupl ,  Erhard Landgraf ,  Richard Luyken ,  Wolfgang Roesner ,  Thomas Schulz ,  Michael Specht

    发明人： Andrew Graham ,  Franz Hofmann ,  Wolfgang Honlein ,  Johannes Kretz ,  Franz Kreupl ,  Erhard Landgraf ,  Richard Luyken ,  Wolfgang Roesner ,  Thomas Schulz ,  Michael Specht

    IPC分类号： G11C13/02 ,  H01L29/78 ,  H01L51/00 ,  H01L51/30 ,  H01L29/76

    CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C2213/17 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/0512

    摘要： Integrated circuit array having field effect transistors (FETs) formed next to and/or above one another. The array has a substrate, a planarized first wiring plane with interconnects and first source/drain regions of the FETs, a planarized first insulator layer on the first wiring plane, a planarized gate region layer, which has patterned gate regions made of electrically conductive material and insulator material introduced therebetween, on the first insulated layer, a planarized second insulator layer on the gate region layer, holes formed through the second insulator layer, the gate regions, and the first insulator layer, a vertical nanoelement serving as a channel region in each of the holes, a second wiring plane with interconnects and second source/drain regions of the FETs, each nanoelement being arranged between the first and second wiring planes, and a gate insulating layer between the respective vertical nanoelement and the electrically conductive material of the gate regions.

    摘要翻译： 集成电路阵列具有形成在彼此之上和/或彼此之上的场效应晶体管（FET）。 阵列具有衬底，具有互连的平坦化的第一布线面和FET的第一源极/漏极区，在第一布线平面上的平坦化的第一绝缘体层，平坦化的栅极区域层，其具有由导电材料制成的图案化栅极区域 和介于其间的绝缘体材料，在所述第一绝缘层上，在所述栅极区域层上的平坦化的第二绝缘体层，穿过所述第二绝缘体层，所述栅极区域和所述第一绝缘体层形成的空穴，用作所述沟道区域中的沟道区域的垂直纳米元件 每个孔，具有互连的第二布线面和FET的第二源极/漏极区，每个纳米元件布置在第一和第二布线平面之间，并且在相应的垂直纳米元件和导电材料之间的栅极绝缘层 门区域。

    High-density NROM-FINFET
    3.
    发明授权
    High-density NROM-FINFET 失效
    高密度NROM-FINFET

    公开(公告)号：US07208794B2

    公开(公告)日：2007-04-24

    申请号：US11073017

    申请日：2005-03-04

    申请人： Franz Hofmann ,  Erhard Landgraf ,  Richard Johannes Luyken ,  Wolfgang Roesner ,  Michael Specht

    发明人： Franz Hofmann ,  Erhard Landgraf ,  Richard Johannes Luyken ,  Wolfgang Roesner ,  Michael Specht

    IPC分类号： H01L29/76 ,  H01L29/788 ,  H01L29/792 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L21/28273 ,  G11C16/0466 ,  H01L21/28282 ,  H01L21/845 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7881 ,  H01L29/792 ,  Y10S257/903 ,  Y10S257/904 ,  Y10S257/905

    摘要： Semiconductor memory having memory cells, each including first and second conductively-doped contact regions and a channel region arranged between the latter, formed in a web-like rib made of semiconductor material and arranged one behind the other in this sequence in the longitudinal direction of the rib. The rib has an essentially rectangular shape with an upper side of the rib and rib side faces lying opposite. A memory layer is configured for programming the memory cell, arranged on the upper side of the rib spaced apart by a first insulator layer, and projects in the normal direction of the one rib side face over one of the rib side faces so that the one rib side face and the upper side of the rib form an edge for injecting charge carriers from the channel region into the memory layer. A gate electrode is spaced apart from the one rib side face by a second insulator layer and from the memory layer by a third insulator layer, electrically insulated from the channel region, and configured to control its electrical conductivity.

    摘要翻译： 具有存储单元的半导体存储器，每个存储单元包括第一和第二导电掺杂的接触区域和布置在其间的沟道区域，所述沟道区域形成在由半导体材料制成的网状肋状物中， 肋骨 肋具有基本上矩形的形状，肋的上侧和肋侧面相对。 存储层被配置为对存储单元进行编程，布置在由第一绝缘体层间隔开的肋的上侧，并且沿着一个肋侧面的一个肋侧面的法线方向突出，使得一个 肋侧面和肋的上侧形成用于将电荷载流子从沟道区域注入到存储层中的边缘。 栅电极通过第二绝缘体层与一个肋侧面间隔开，并且通过与沟道区电绝缘并且被配置为控制其导电性的第三绝缘体层与存储层隔开。

    Fin field effect transistor arrangement and method for producing a fin field effect transistor arrangement
    7.
    发明授权
    Fin field effect transistor arrangement and method for producing a fin field effect transistor arrangement 有权
    翅片场效应晶体管布置及其制造方法

    公开(公告)号：US07719059B2

    公开(公告)日：2010-05-18

    申请号：US11588868

    申请日：2006-10-27

    申请人： Franz Hofmann ,  Erhard Landgraf ,  Richard Johannes Luyken

    发明人： Franz Hofmann ,  Erhard Landgraf ,  Richard Johannes Luyken

    IPC分类号： H01L21/84 ,  H01L21/8238 ,  H01L27/12

    CPC分类号： H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78636

    摘要： A fin field effect transistor arrangement comprises a substrate and a first fin field effect transistor on and/or in the substrate. The first fin field effect transistor includes a fin in which a channel region is formed between a first source/drain region and a second source/drain region and above which a gate region is formed. A second fin field effect transistor is provided on and/or in the substrate including a fin in which a channel region is formed between a first source/drain region and a second source/drain region and above which a gate region is formed. The second fin field effect transistor is arranged laterally alongside the first fin field effect transistor, wherein a height of the fin of the first fin field effect transistor is greater than a height of the fin of the second fin field effect transistor.

    摘要翻译： 鳍状场效应晶体管布置包括衬底和衬底上和/或衬底中的第一鳍状场效应晶体管。 第一鳍状场效应晶体管包括鳍状物，其中在第一源极/漏极区域和第二源极/漏极区域之间形成沟道区域，并且在其上形成栅极区域。 第二鳍状场效应晶体管设置在衬底上和/或衬底中，包括在第一源极/漏极区域和第二源极/漏极区域之间形成沟道区域的鳍片，并且在其上形成栅极区域。 第二鳍状场效应晶体管沿第一鳍状场效应晶体管横向布置，其中第一鳍状场效应晶体管的鳍的高度大于第二鳍状场效应晶体管的鳍的高度。

    NROM semiconductor memory device and fabrication method
    8.
    发明授权
    NROM semiconductor memory device and fabrication method 失效
    NROM半导体存储器件及其制造方法

    公开(公告)号：US07344923B2

    公开(公告)日：2008-03-18

    申请号：US11282904

    申请日：2005-11-18

    申请人： Franz Hofmann ,  Erhard Landgraf ,  Michael Specht

    发明人： Franz Hofmann ,  Erhard Landgraf ,  Michael Specht

    IPC分类号： H01L21/82

    CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/7923

    摘要： An NROM semiconductor memory device and fabrication method are disclosed. According to one aspect, a method for fabricating an NROM semiconductor memory device can include providing a plurality of u-shaped MOSFETs, which are spaced apart from one another and have a multilayer dielectric. The dielectric suitable for charge trapping along rows in a first direction and alone columns in a second direction in trenches of a semiconductor substrate. Source/drain regions are provided between the u-shaped MOSFETs in interspaces between the rows which run parallel to the columns. Isolation trenches are provided in the source/drain regions between the u-shaped MOSFETs of adjacent columns as far as a particular depth in the semiconductor substrate. The isolation trenches are filled with an insulation material. Word lines are provided for connecting respective rows of u-shaped MOSFETs.

    摘要翻译： 公开了一种NROM半导体存储器件及其制造方法。 根据一个方面，一种用于制造NROM半导体存储器件的方法可以包括提供多个彼此间隔开并具有多层电介质的u形MOSFET。 适合于在半导体衬底的沟槽中沿着第一方向沿着行电荷捕获并在第二方向上单独的列的电介质。 源极/漏极区域设置在平行于列的行之间的间隔中的u形MOSFET之间。 在相邻列的u形MOSFET之间的源极/漏极区域中提供了直到半导体衬底中的特定深度的隔离沟槽。 隔离槽填充绝缘材料。 字线用于连接各行的u形MOSFET。

    Fabrication method for memory cell
    9.
    发明授权
    Fabrication method for memory cell 失效
    存储单元制造方法

    公开(公告)号：US06982202B2

    公开(公告)日：2006-01-03

    申请号：US10899436

    申请日：2004-07-26

    申请人： Franz Hofmann ,  Erhard Landgraf ,  Hannes Luyken

    发明人： Franz Hofmann ,  Erhard Landgraf ,  Hannes Luyken

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792

    摘要： Method of fabricating a memory cell, in which a storage layer, which is designed for programming by charge carrier trapping, and a gate electrode, which is electrically insulated from a semiconductor material, are fabricated at a top side of a semiconductor body or a semiconductor layer structure above a channel region provided between doped source-drain regions. The method includes the steps of fabricating at least one trench in the top side, providing at least portions of the trench walls which adjoin the source-drain regions to be fabricated with the storage layer, depositing a material provided for the gate electrode into the trench, forming the source-drain regions by covering the gate electrode, removing, on both sides of the trench, the semiconductor material down to an intended depth, and implanting dopant, and applying an insulation layer to the source-drain region, and fabricating an electrical connection for the gate electrode.

    摘要翻译： 制造存储单元的方法，其中设计用于通过电荷载流子捕获进行编程的存储层和与半导体材料电绝缘的栅电极制造在半导体本体或半导体的顶侧 在设置在掺杂源极 - 漏极区之间的沟道区域之上的层结构。 该方法包括以下步骤：在顶侧制造至少一个沟槽，提供沟槽壁的至少部分，其邻接待制造的源极 - 漏极区域与存储层，将为栅电极提供的材料沉积到沟槽 通过覆盖栅极电极形成源极 - 漏极区域，在沟槽的两侧将半导体材料去除到预期深度，并且注入掺杂剂，并且向源极 - 漏极区域施加绝缘层，并且制造 栅电极的电连接。