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1.发明授权Non-volatile memory cell, memory cell arrangement and method for production of a non-volatile memory cell 有权非易失性存储单元，存储单元布置和用于生产非易失性存储单元的方法公开(公告)号：US07265376B2
公开(公告)日：2007-09-04
申请号：US10533215
申请日：2003-10-29
申请人： Andrew Graham , Franz Hofmann , Wolfgang Hönlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Richard Johannes Luyken , Wolfgang Rösner , Thomas Schulz , Michael Specht
发明人： Andrew Graham , Franz Hofmann , Wolfgang Hönlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Richard Johannes Luyken , Wolfgang Rösner , Thomas Schulz , Michael Specht
IPC分类号： H01L35/24 , H01L51/00 , H01L29/788 , H01L21/336
CPC分类号： H01L29/7888 , B82Y10/00 , G11C13/025 , G11C2213/17 , H01L21/28282 , H01L21/84 , H01L27/115 , H01L27/11568 , H01L27/1203 , H01L27/28 , H01L29/66833 , H01L29/792 , H01L29/7926 , H01L51/0048 , H01L51/0052 , H01L51/057
摘要： A nonvolatile memory cell, memory cell arrangement, and method for production of a nonvolatile memory cell is disclosed. The nonvolatile memory cell includes a vertical field-effect transistor (FET). The FET contains a nanoelement arranged as a channel region and an electrically insulating layer. The electrically insulating layer at least partially surrounds the nanoelement and acts as a charge storage layer and as a gate-insulating layer. The electrically insulating layer is arranged such that electrical charge carriers may be selectively introduced into or removed from the electrically insulating layer and the electrical conductivity characteristics of the nanoelement may be influenced by the electrical charge carriers introduced into the electrically insulating layer.
摘要翻译： 公开了一种用于制造非易失性存储单元的非易失性存储单元，存储单元布置和方法。 非易失性存储单元包括垂直场效应晶体管（FET）。 FET包含布置为沟道区和电绝缘层的纳米元件。 电绝缘层至少部分地包围纳米元件并充当电荷存储层和作为栅极绝缘层。 电绝缘层被布置成使得电荷载体可以被选择性地引入到电绝缘层中或从电绝缘层移除，并且纳米元件的导电特性可能受到引入电绝缘层中的电荷载流子的影响。
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公开(公告)号：US06730930B2
公开(公告)日：2004-05-04
申请号：US10275598
申请日：2003-04-21
IPC分类号： H01L3524
CPC分类号： H01L27/28 , B82Y10/00 , G11C13/0014 , G11C13/0016 , G11C2213/77 , H01L51/0575
摘要： A memory element with organic material comprises two metallized layers, arranged one on top of the other, with first lines and second lines which are arranged to intersect with each other. A channel is formed at the intersections between the first line and the second line, which overlaps the first line partially and completely overlaps the second line. The channels are filled with a filling material, the electrical conductivity of which may be altered by an applied electrical voltage.
摘要翻译： 具有有机材料的存储元件包括两个金属化层，其一个在另一个的顶部上，第一线和第二线被布置为彼此相交。 在第一线和第二线之间的交叉处形成通道，其与第一线重叠，并且与第二线完全重叠。 通道填充有填充材料，其电导率可以通过施加的电压而改变。
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3.发明授权公开(公告)号：US07189988B2
公开(公告)日：2007-03-13
申请号：US10482719
申请日：2002-07-01
IPC分类号： H01L35/24
CPC分类号： G11C13/0019 , B82Y10/00 , G11C13/0014 , H01L51/0048 , H01L51/005 , H01L51/0052 , H01L51/0093 , H01L51/0595
摘要： The invention relates to a molecular electronics arrangement comprising a substrate, at least one first strip conductor having a surface and being arranged in or on the substrate, a spacer which is arranged on the surface of the at least one first strip conductor and which partially covers the surface of the at least one first strip conductor, and at least one second strip conductor which is arranged on the spacer and comprises a surface which faces the surface of the at least one first strip conductor in a plane manner. The spacer partially covers the surface of the at least one second strip conductor, and defines a pre-determined distance between the at least one first strip conductor and the at least one second strip conductor. The inventive molecular electronics arrangement also comprises molecular electronics molecules which are arranged between a free region of the surface of the at least one first strip conductor and a free region of the surface of the at least one second strip conductor, the length of said molecules being essentially equal to the distance between the at least one first strip conductor and the at least one second strip conductor. The invention also relates to a method for producing a molecular electronics arrangement.
摘要翻译： 本发明涉及一种分子电子装置，其包括基底，至少一个具有表面并且布置在基底中或基底上的第一条状导体，隔离物，其被布置在至少一个第一条状导体的表面上，并且部分覆盖 所述至少一个第一带状导体的表面和布置在所述间隔件上并包括以平面方式面对所述至少一个第一带状导体的表面的表面的至少一个第二条状导体。 所述间隔件部分地覆盖所述至少一个第二条状导体的表面，并且限定所述至少一个第一条状导体和所述至少一个第二条状导体之间的预定距离。 本发明的分子电子学装置还包括分子电子学分子，其分布在至少一个第一带状导体的表面的自由区域和至少一个第二条状导体的表面的自由区域之间，所述分子的长度为 基本上等于所述至少一个第一带状导体和所述至少一个第二带状导体之间的距离。 本发明还涉及生产分子电子装置的方法。
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4.发明授权Method for the production of a memory cell, memory cell and memory cell arrangement 有权用于生产存储器单元，存储单元和存储单元布置的方法公开(公告)号：US07195978B2
公开(公告)日：2007-03-27
申请号：US10999810
申请日：2004-11-29
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L21/28273 , G11C16/0416 , G11C16/0483 , H01L21/28282 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L27/1203 , H01L29/66825 , H01L29/7881 , H01L29/7883
摘要： Memory cell having an auxiliary substrate, on which a first gate insulating layer is formed, a floating gate formed on the first gate insulating layer, an electrically insulating layer formed on the floating gate, a memory gate electrode formed on the electrically insulating layer, a substrate fixed to the memory gate electrode, a second gate insulating layer formed on a part of a surface of the auxiliary substrate, which surface is uncovered by partially removing the auxiliary substrate, a read gate electrode formed on the second gate insulating layer, and two source/drain regions located essentially in a surface region of the remaining material of the auxiliary substrate that is free of the second gate insulating layer and the read gate electrode, a channel region located between the two source/drain regions, wherein the channel region at least partly laterally overlaps the floating gate and the read gate electrode.
摘要翻译： 具有辅助基板的存储单元，其上形成有第一栅极绝缘层，形成在第一栅极绝缘层上的浮动栅极，形成在浮动栅极上的电绝缘层，形成在电绝缘层上的存储栅电极， 基板固定到存储栅电极，第二栅极绝缘层，形成在辅助基板的表面的一部分上，该表面通过部分去除辅助基板而被覆盖，形成在第二栅极绝缘层上的读取栅电极和两个 源极/漏极区域基本上位于辅助衬底的不含第二栅极绝缘层和读取栅电极的剩余材料的表面区域中，位于两个源极/漏极区域之间的沟道区域，其中沟道区域在 至少部分地侧向重叠浮置栅极和读取栅电极。
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公开(公告)号：US06977413B2
公开(公告)日：2005-12-20
申请号：US10220344
申请日：2001-03-08
IPC分类号： H01L21/336 , H01L29/423 , H01L29/786 , H01L29/76
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795 , H01L29/78651
摘要： The bar-type field effect transistor consists of a substrate, a bar placed above a substrate and a gate and spacer placed above part of the bar.
摘要翻译： 棒式场效应晶体管由衬底，放置在衬底上方的棒和位于棒的一部分上方的栅极和间隔件组成。
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6.发明授权Integrated read-only memory, method for operating said read-only memory and corresponding production method 有权集成只读存储器，用于操作所述只读存储器的方法和相应的制造方法公开(公告)号：US07307865B2
公开(公告)日：2007-12-11
申请号：US10505320
申请日：2003-02-17
IPC分类号： G11C17/00
CPC分类号： H01L27/28 , H01L27/2436 , H01L27/2454 , H01L27/2472 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/14 , H01L45/147
摘要： An integrated read-only memory having select transistors, each of which has a drain connection and an electrode connection for feeding an electrical signal such as a voltage or a current. A layer is provided between the drain connections and the electrode, whose electric resistance can be changed under the effect of a configuration voltage or current. The layer may be applied in a backend process.
摘要翻译： 具有选择晶体管的集成只读存储器，每个具有漏极连接和用于馈送诸如电压或电流的电信号的电极连接。 在漏极连接和电极之间设置一层，其电阻可以在配置电压或电流的作用下改变。 该层可以应用在后端进程中。
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公开(公告)号：US07829892B2
公开(公告)日：2010-11-09
申请号：US11926653
申请日：2007-10-29
申请人： Richard Johannes Luyken , Franz Hofmann , Lothar Risch , Dirk Manger , Wolfgang Roesner , Till Schloesser , Michael Specht
发明人： Richard Johannes Luyken , Franz Hofmann , Lothar Risch , Dirk Manger , Wolfgang Roesner , Till Schloesser , Michael Specht
IPC分类号： H01L29/12
CPC分类号： H01L27/10823 , H01L27/10808 , H01L27/10826 , H01L27/10829 , H01L27/10891 , H01L29/7851
摘要： An integrated circuit including a gate electrode is disclosed. One embodiment provides a transistor including a first source/drain electrode and a second source/drain electrode. A channel is arranged between the first and the second source/drain electrode in a semiconductor substrate. A gate electrode is arranged adjacent the channel layer and is electrically insulated from the channel layer. A semiconductor substrate electrode is provided on a rear side. The gate electrode encloses the channel layer at least two opposite sides.
摘要翻译： 公开了一种包括栅电极的集成电路。 一个实施例提供一种晶体管，其包括第一源极/漏极电极和第二源极/漏极电极。 在半导体衬底中的第一和第二源极/漏极之间布置有沟道。 栅电极被布置在沟道层附近并且与沟道层电绝缘。 半导体基板电极设置在后侧。 栅极电极将沟道层包围至少两个相对的侧面。
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公开(公告)号：US07611928B2
公开(公告)日：2009-11-03
申请号：US10968846
申请日：2004-10-18
IPC分类号： H01L21/00
CPC分类号： H01L21/76254
摘要： Substrate having a first partial substrate with a carrier layer and a second partial substrate, which is bonded to the first partial substrate. The second partial substrate has an insulator layer, which is applied on the carrier layer and has at least two regions each having a different thickness, thereby forming a stepped surface of the insulator layer, and a semiconductor layer, which is applied to the stepped surface of the insulator layer and is formed at least partially epitaxially, wherein the semiconductor layer has a planar surface which is opposite to the stepped surface of the insulator layer. Transistors are formed on the semiconductor layer.
摘要翻译： 衬底，具有第一部分衬底和载体层，第二部分衬底与第一部分衬底结合。 第二部分基板具有绝缘体层，其被施加在载体层上并且具有至少两个各自具有不同厚度的区域，从而形成绝缘体层的台阶表面，以及施加到台阶表面的半导体层 并且至少部分地外延形成，其中半导体层具有与绝缘体层的台阶表面相对的平面。 在半导体层上形成晶体管。
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9.发明授权Semiconductor memory component with body region of memory cell having a depression and a graded dopant concentration 失效具有存储单元体区域的半导体存储器组件具有凹陷和渐变的掺杂剂浓度公开(公告)号：US07598543B2
公开(公告)日：2009-10-06
申请号：US11438883
申请日：2006-05-23
IPC分类号： H01L27/108
CPC分类号： H01L27/108 , H01L27/10802 , H01L27/1203
摘要： A semiconductor memory component comprises at least one memory cell. The memory cell comprises a semiconductor body comprised of a body region, a drain region and a source region, a gate dielectric, and a gate electrode. The body region comprises a first conductivity type and a depression between the source and drain regions, and the source and drain regions comprise a second conductivity type. The gate electrode is arranged at least partly in the depression and is insulated from the body, source, and drain regions by the gate dielectric. The body region further comprises a first continuous region with a first dopant concentration and a second continuous region with a second dopant concentration greater than the first dopant concentration. The first continuous region adjoins the drain region, the depression and the source region, and the second region is arranged below the first region and adjoins the first region.
摘要翻译： 半导体存储器组件包括至少一个存储单元。 存储单元包括由体区，漏区和源区组成的半导体本体，栅电介质和栅电极。 主体区域包括第一导电类型和源极和漏极区域之间的凹陷，并且源极和漏极区域包括第二导电类型。 栅电极至少部分地布置在凹陷中，并且通过栅极电介质与主体，源极和漏极区绝缘。 体区还包括具有第一掺杂剂浓度的第一连续区域和具有大于第一掺杂剂浓度的第二掺杂剂浓度的第二连续区域。 第一连续区域邻接漏极区域，凹陷部分和源极区域，并且第二区域布置在第一区域下方并与第一区域相邻。
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公开(公告)号：US07208794B2
公开(公告)日：2007-04-24
申请号：US11073017
申请日：2005-03-04
IPC分类号： H01L29/76 , H01L29/788 , H01L29/792 , H01L29/94 , H01L31/119
CPC分类号： H01L21/28273 , G11C16/0466 , H01L21/28282 , H01L21/845 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L27/1203 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7881 , H01L29/792 , Y10S257/903 , Y10S257/904 , Y10S257/905
摘要： Semiconductor memory having memory cells, each including first and second conductively-doped contact regions and a channel region arranged between the latter, formed in a web-like rib made of semiconductor material and arranged one behind the other in this sequence in the longitudinal direction of the rib. The rib has an essentially rectangular shape with an upper side of the rib and rib side faces lying opposite. A memory layer is configured for programming the memory cell, arranged on the upper side of the rib spaced apart by a first insulator layer, and projects in the normal direction of the one rib side face over one of the rib side faces so that the one rib side face and the upper side of the rib form an edge for injecting charge carriers from the channel region into the memory layer. A gate electrode is spaced apart from the one rib side face by a second insulator layer and from the memory layer by a third insulator layer, electrically insulated from the channel region, and configured to control its electrical conductivity.
摘要翻译： 具有存储单元的半导体存储器，每个存储单元包括第一和第二导电掺杂的接触区域和布置在其间的沟道区域，所述沟道区域形成在由半导体材料制成的网状肋状物中， 肋骨 肋具有基本上矩形的形状，肋的上侧和肋侧面相对。 存储层被配置为对存储单元进行编程，布置在由第一绝缘体层间隔开的肋的上侧，并且沿着一个肋侧面的一个肋侧面的法线方向突出，使得一个 肋侧面和肋的上侧形成用于将电荷载流子从沟道区域注入到存储层中的边缘。 栅电极通过第二绝缘体层与一个肋侧面间隔开，并且通过与沟道区电绝缘并且被配置为控制其导电性的第三绝缘体层与存储层隔开。
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