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    Semiconductor memory device
    101.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US12052855B2

    公开(公告)日：2024-07-30

    申请号：US18165692

    申请日：2023-02-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hui-Jung Kim ,  Taehyun An ,  Kiseok Lee ,  Keunnam Kim ,  Yoosang Hwang

    IPC: H10B12/00 ,  G11C5/06

    CPC classification number: H10B12/30 ,  G11C5/063

    Abstract: A semiconductor memory device includes a stack including a plurality of layers vertically stacked on a substrate, each of the layers including a bit line extending in a first direction and a semiconductor pattern extending from the bit line in a second direction crossing the first direction, a gate electrode along each of the semiconductor patterns stacked, a vertical insulating layer on the gate electrode, a stopper layer, and a data storing element electrically connected to each of the semiconductor patterns. The data storing element includes a first electrode electrically connected to each of the semiconductor patterns, a second electrode on the first electrode, and a dielectric layer between the first and second electrodes. The stopper layer is between the vertical insulating layer and the second electrode.

    Semiconductor devices
    103.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US11706910B2

    公开(公告)日：2023-07-18

    申请号：US17229942

    申请日：2021-04-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyosub Kim ,  Keunnam Kim ,  Manbok Kim ,  Soojeong Kim ,  Chulkwon Park ,  Seungbae Jeon ,  Yoosang Hwang

    IPC: H10B12/00

    CPC classification number: H10B12/315 ,  H10B12/0335 ,  H10B12/053 ,  H10B12/34 ,  H10B12/482

    Abstract: Semiconductor devices may include an active pattern, a gate structure in an upper portion of the active pattern, a bit line structure on the active pattern, a lower spacer structure on a lower portion of a sidewall of the bit line structure, and an upper spacer structure on an upper portion of the sidewall of the bit line structure. The lower spacer structure includes first and second lower spacers sequentially stacked, the first lower spacer contacts the lower portion of the sidewall of the bit line structure and does not include nitrogen, and the second lower spacer includes a material different from the first lower spacer. A portion of the upper spacer structure contacting the upper portion of the sidewall of the bit line structure includes a material different from the first lower spacer.

    SEMICONDUCTOR MEMORY DEVICE
    104.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20230189501A1

    公开(公告)日：2023-06-15

    申请号：US18165692

    申请日：2023-02-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hui-Jung KIM ,  Taehyun An ,  Kiseok Lee ,  Yoosang Hwang

    IPC: H10B12/00 ,  G11C5/06

    CPC classification number: H10B12/30 ,  G11C5/063

    Abstract: A semiconductor memory device includes a stack including a plurality of layers vertically stacked on a substrate, each of the layers including a bit line extending in a first direction and a semiconductor pattern extending from the bit line in a second direction crossing the first direction, a gate electrode along each of the semiconductor patterns stacked, a vertical insulating layer on the gate electrode, a stopper layer, and a data storing element electrically connected to each of the semiconductor patterns. The data storing element includes a first electrode electrically connected to each of the semiconductor patterns, a second electrode on the first electrode, and a dielectric layer between the first and second electrodes. The stopper layer is between the vertical insulating layer and the second electrode.

    Semiconductor device and manufacturing method of the same
    106.
    发明授权
    Semiconductor device and manufacturing method of the same 有权

    公开(公告)号：US11616066B2

    公开(公告)日：2023-03-28

    申请号：US17384347

    申请日：2021-07-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyosub Kim ,  Keunnam Kim ,  Dongoh Kim ,  Bongsoo Kim ,  Euna Kim ,  Chansic Yoon ,  Kiseok Lee ,  Hyeonok Jung ,  Sunghee Han ,  Yoosang Hwang

    IPC: H01L27/108 ,  H01L23/528

    Abstract: A semiconductor device includes: an active region defined by a device isolation layer formed in a substrate; a word line configured to cross the active region, the word line extending in a first direction and being formed in the substrate; a bit line extending in a second direction perpendicular to the first direction on the word line; a first contact connecting the bit line to the active region; a first mask for forming the active region, the first mask being formed on the active region; and a second mask of which a height of a top surface thereof is greater than a height of a top surface of the active region, the second mask covering the word line, wherein the active region has a bar shape that extends to form an acute angle with respect to the first direction.

    Semiconductor memory device
    107.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US11600620B2

    公开(公告)日：2023-03-07

    申请号：US17353398

    申请日：2021-06-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Il Han ,  Sunghee Han ,  Yoosang Hwang

    IPC: H01L27/108

    Abstract: A semiconductor memory device is provided. The device includes a substrate including a cell region and a peripheral region; a plurality of lower electrodes disposed on the substrate in the cell region; a dielectric layer disposed on the plurality of lower electrodes; a metal containing layer disposed on the dielectric layer; a silicon germanium layer disposed on and electrically connected to the metal containing layer; a conductive pad disposed on and electrically connected to the silicon germanium layer; and an upper electrode contact plug disposed on and electrically connected to the conductive pad; The conductive pad extends from the upper electrode contact plug towards the peripheral region in a first direction, and the silicon germanium layer includes an edge portion that extends past the conductive pad in the first direction.

    Semiconductor memory device
    108.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US11587929B2

    公开(公告)日：2023-02-21

    申请号：US16880230

    申请日：2020-05-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hui-Jung Kim ,  Taehyun An ,  Kiseok Lee ,  Keunnam Kim ,  Yoosang Hwang

    IPC: H01L27/108 ,  G11C5/06

    Abstract: A semiconductor memory device includes a stack including a plurality of layers vertically stacked on a substrate, each of the layers including a bit line extending in a first direction and a semiconductor pattern extending from the bit line in a second direction crossing the first direction, a gate electrode along each of the semiconductor patterns stacked, a vertical insulating layer on the gate electrode, a stopper layer, and a data storing element electrically connected to each of the semiconductor patterns. The data storing element includes a first electrode electrically connected to each of the semiconductor patterns, a second electrode on the first electrode, and a dielectric layer between the first and second electrodes. The stopper layer is between the vertical insulating layer and the second electrode.

    Semiconductor memory devices
    109.
    发明授权
    Semiconductor memory devices 有权

    公开(公告)号：US11569239B2

    公开(公告)日：2023-01-31

    申请号：US17126195

    申请日：2020-12-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiseok Lee ,  Bong-Soo Kim ,  Jiyoung Kim ,  Hui-Jung Kim ,  Seokhan Park ,  Hunkook Lee ,  Yoosang Hwang

    IPC: H01L27/108 ,  H01L23/528 ,  H01L29/08 ,  H01L29/165 ,  H01L29/10 ,  H01L23/522 ,  H01L49/02

    Abstract: Semiconductor memory devices may include first and second stacks on a substrate and first and second interconnection lines on the first and second stacks. Each of the first and second stacks may include semiconductor patterns vertically stacked on the substrate, conductive lines connected to the semiconductor patterns, respectively, and a gate electrode that is adjacent to the semiconductor patterns and extends in a vertical direction. The first stack may include a first conductive line and a first gate electrode, and the second stack may include a second conductive line and a second gate electrode. Lower surfaces of the first and second conductive lines may be coplanar. The first interconnection line may be electrically connected to at least one of the first and second conductive lines. The second interconnection line may be electrically connected to at least one of the first and second gate electrodes.

    Three-dimensional semiconductor memory device
    110.
    发明授权
    Three-dimensional semiconductor memory device 有权

    公开(公告)号：US11502084B2

    公开(公告)日：2022-11-15

    申请号：US16986367

    申请日：2020-08-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Joongchan Shin ,  Changkyu Kim ,  Hui-Jung Kim ,  Iljae Shin ,  Taehyun An ,  Kiseok Lee ,  Eunju Cho ,  Hyungeun Choi ,  Sung-Min Park ,  Ahram Lee ,  Sangyeon Han ,  Yoosang Hwang

    IPC: H01L27/108 ,  H01L23/528 ,  H01L21/822

    Abstract: A three-dimensional semiconductor memory device includes first semiconductor patterns, which are vertically spaced apart from each other on a substrate, each of which includes first and second end portions spaced apart from each other, and first and second side surfaces spaced apart from each other to connect the first and second end portions, first and second source/drain regions disposed in each of the first semiconductor patterns and adjacent to the first and second end portions, respectively, a channel region in each of the first semiconductor patterns and between the first and second source/drain regions, a first word line adjacent to the first side surfaces and the channel regions and vertically extended, and a gate insulating layer interposed between the first word line and the first side surfaces. The gate insulating layer may be extended to be interposed between the first source/drain regions.

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