公开(公告)号：US11075179B2

公开(公告)日：2021-07-27

申请号：US16430075

申请日：2019-06-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Hao Cheng ,  Yen-Yu Chen ,  Chih-Wei Lin ,  Yi-Ming Dai

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/522

Abstract: A method for forming a bond pad structure includes forming an interconnect structure on a semiconductor device, forming a passivation layer on the interconnect structure, forming at least one opening through the passivation layer, forming an oxidation layer at least in the opening, and forming a pad metal layer on the oxidation layer. A portion of the interconnect structure is exposed by the at least one opening.

公开(公告)号：US11075131B2

公开(公告)日：2021-07-27

申请号：US16547579

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Da Tsai ,  Ching-Hua Hsieh ,  Chih-Wei Lin ,  Tsai-Tsung Tsai ,  Sheng-Chieh Yang ,  Chia-Min Lin

IPC: H01L23/29 ,  H01L21/56 ,  H01L21/3105 ,  H01L23/532

Abstract: A semiconductor package including a semiconductor die, a molding compound and a redistribution structure is provided. The molding compound laterally wraps around the semiconductor die, wherein the molding compound includes a base material and a first filler particle and a second filler particle embedded in the base material. The first filler particle has a first recess located in a top surface of the first filler particle, and the second filler particle has at least one hollow void therein. The redistribution structure is disposed on the semiconductor die and the molding compound, wherein the redistribution structure has a polymer dielectric layer. The polymer dielectric layer includes a body portion and a first protruding portion protruding from the body portion, wherein the body portion is in contact with the base material and the top surface of the first filler particle, and the first protruding portion fits with the first recess of the first filler particle.

公开(公告)号：US20210202335A1

公开(公告)日：2021-07-01

申请号：US17201445

申请日：2021-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chung-Shi Liu ,  Chih-Fan Huang ,  Chih-Wei Lin ,  Wei-Hung Lin ,  Ming-Da Cheng

IPC: H01L23/31 ,  H01L25/10 ,  H01L21/56 ,  H01L23/528 ,  H01L21/768 ,  H01L21/82 ,  H01L23/04 ,  H01L23/367 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498

Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die, a molding compound disposed around the integrated circuit die, and an interconnect structure disposed over the integrated circuit die and the molding compound. The molding compound is thicker than the integrated circuit die.

公开(公告)号：US20210118665A1

公开(公告)日：2021-04-22

申请号：US17114178

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jen-Ti Wang ,  Chih-Wei Lin ,  Fu-Hsien Li ,  Yi-Ming Chen ,  Cheng-Ho Hung

IPC: H01L21/02 ,  H01L21/66 ,  G01B11/24 ,  G01N33/00 ,  H01L21/673 ,  H01L21/677 ,  B23P6/00

Abstract: An apparatus for semiconductor manufacturing includes an input port to receive a carrier, wherein the carrier includes a carrier body, a housing installed onto the carrier body, and a filter installed between the carrier body and the housing. The apparatus further includes a first robotic arm to uninstall the housing from the carrier and to reinstall the housing into the carrier; one or more second robotic arms to remove the filter from the carrier and to install a new filter into the carrier; and an output port to release the carrier to production.

公开(公告)号：US10916517B2

公开(公告)日：2021-02-09

申请号：US16727628

申请日：2019-12-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Wei Bih ,  Sheng-Wei Yeh ,  Yen-Yu Chen ,  Wen-Hao Cheng ,  Chih-Wei Lin ,  Chun-Chih Lin

IPC: H01L23/532 ,  H01L23/525 ,  H01L21/02 ,  H01L23/00

Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.

公开(公告)号：US20200338796A1

公开(公告)日：2020-10-29

申请号：US16398164

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Feng Weng ,  Ching-Hua Hsieh ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Sheng-Hsiang Chiu ,  Yao-Tong Lai ,  Chia-Min Lin

IPC: B29C45/14 ,  B29C45/00 ,  B29C45/03 ,  H01L21/56

Abstract: A molding apparatus is configured for molding a semiconductor device and includes a lower mold and an upper mold. The lower mold is configured to carry the semiconductor device. The upper mold is disposed above the lower mold for receiving the semiconductor device and includes a mold part and a dynamic part. The mold part is configured to cover the upper surface of the semiconductor device. The dynamic part is disposed around a device receiving region of the upper mold and configured to move relatively to the mold part. A molding method and a molded semiconductor device are also provided.

公开(公告)号：US10510709B2

公开(公告)日：2019-12-17

申请号：US15491986

申请日：2017-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Tse Chen ,  Ching-Hua Hsieh ,  Chung-Shi Liu ,  Chih-Wei Lin

IPC: H01L23/12 ,  H01L23/00 ,  H01L21/683 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has at least one chip, through interlayer vias aside the chip and a composite molding compound encapsulating the chip and the through interlayer vias. The semiconductor package may further include a redistribution layer and conductive elements disposed on the redistribution layer.

公开(公告)号：US10439022B2

公开(公告)日：2019-10-08

申请号：US15830979

申请日：2017-12-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lin ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.

公开(公告)号：US10354965B2

公开(公告)日：2019-07-16

申请号：US15719370

申请日：2017-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Wei Bih ,  Chun-Chih Lin ,  Sheng-Wei Yeh ,  Yen-Yu Chen ,  Chih-Wei Lin ,  Wen-Hao Cheng

IPC: H01L23/52 ,  H01L23/00

Abstract: The present disclosure describes an bonding pad formation method that incorporates an tantalum (Ta) conductive layer to block mobile ionic charges generated during the aluminum-copper (AlCu) metal fill deposition. For example, the method includes forming one or more interconnect layers over a substrate and forming a dielectric over a top interconnect layer of the one or more interconnect layers. A first recess is formed in the dielectric to expose a line or a via from the top interconnect layer. A conductive layer is formed in the first recess to form a second recess that is smaller than the first recess. A barrier metal layer is formed in the second recess to form a third recess that is smaller than the second recess. A metal is formed to fill the third recess.

公开(公告)号：US20190139845A1

公开(公告)日：2019-05-09

申请号：US15874890

申请日：2018-01-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Cheng Lin ,  Ching-Hua Hsieh ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Chih-Wei Lin

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/367 ,  H01L23/29 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package including a circuit substrate, an interposer structure, a plurality of dies, and an insulating encapsulant is provided. The interposer structure is disposed on the circuit substrate. The plurality of dies is disposed on the interposer structure, wherein the plurality of dies is electrically connected to the circuit substrate through the interposer structure. The insulating encapsulant is disposed on the circuit substrate, wherein the insulating encapsulant surrounds the plurality of dies and the interposer structure and encapsulates at least the interposer structure, the insulating encapsulant has a groove that surrounds the interposer structure and the plurality of dies, and the interposer structure and the plurality of dies are confined to be located within the groove.