公开(公告)号：US20100128528A1

公开(公告)日：2010-05-27

申请号：US12695559

申请日：2010-01-28

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5641 ,  G11C2211/5648

摘要： One or more embodiments include programming, in parallel, a first cell to one of a first number of states and a second cell to one of a second number of states. Such embodiments include programming, separately, the first cell to one of a third number of states based, at least in part, on the one of the first number of states and the second cell to one of a fourth number of states based, at least in part, on the one of the second number of states.

摘要翻译： 一个或多个实施例包括并行地将第一小区编程为第一数量状态中的一个，将第二小区编程为第二数量的状态中的一个。 这样的实施例包括至少部分地基于至少一个状态的第一数量状态和第二小区中的一个至第四数量的状态来将第一小区单独地编程为第三数量的状态中的一个 部分地是第二个国家之一。

公开(公告)号：US07675778B2

公开(公告)日：2010-03-09

申请号：US11951166

申请日：2007-12-05

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/16 ,  H01L27/115 ,  H01L27/11524

摘要： There is provided a memory array and methods for manufacturing the same. In one embodiment, there is provided a string comprising a plurality of transistors. Each of the plurality of transistors includes: a charge storage node, a control gate, and at least one resistive element coupled to the string. The control gate of at least one of the plurality of transistors can be selectively coupled to a reference potential via a corresponding one of the at least one resistive element.

摘要翻译： 提供了一种存储器阵列及其制造方法。 在一个实施例中，提供了一种包括多个晶体管的串。 多个晶体管中的每一个包括：电荷存储节点，控制栅极和耦合到串的至少一个电阻元件。 多个晶体管中的至少一个的控制栅极可以经由至少一个电阻元件中的对应的一个选择性地耦合到参考电位。

公开(公告)号：US07609549B2

公开(公告)日：2009-10-27

申请号：US12346353

申请日：2008-12-30

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/12

摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for programming an array of non-volatile multilevel memory cells to a number of threshold voltage ranges. One method includes programming a lower page of a first wordline cell to increase a threshold voltage (Vt) of the first wordline cell to a first Vt within a lowermost Vt range. The method includes programming a lower page of a second wordline cell prior to programming an upper page of the first wordline cell. The method includes programming the upper page of the first wordline cell such that the first Vt is increased to a second Vt, wherein the second Vt is within a Vt range which is then a lowermost Vt range and is positive.

公开(公告)号：US07606075B2

公开(公告)日：2009-10-20

申请号：US11407227

申请日：2006-04-19

申请人： Seiichi Aritome ,  Akira Goda

发明人： Seiichi Aritome ,  Akira Goda

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/26 ,  G11C16/0483

摘要： Non-volatile memory devices utilizing a NAND architecture are adapted to perform read operations where a first potential is supplied to source lines associated with a selected block of an array of memory cells and a second, different, potential is supplied to other source lines not associated with that block. By supplying a different potential to source lines of unselected blocks, current leakage can be mitigated.

摘要翻译： 利用NAND架构的非易失性存储器件适于执行读取操作，其中将第一电位提供给与存储器单元阵列的所选块相关联的源极线，并且将第二不同的电位提供给不相关的其它源极线 与那个块。 通过向未选择的块的源极线提供不同的电位，可以减轻电流泄漏。

公开(公告)号：US07539066B2

公开(公告)日：2009-05-26

申请号：US11617516

申请日：2006-12-28

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/14 ,  G11C16/344

摘要： Various embodiments include erasing at least one memory cell of a string of memory cells of a memory device while a control gate of at least one of a first memory cell and a second memory cell of the string of memory cells has a first voltage and while a control gate of each memory cell of a plurality of intermediate memory cells between the first memory cell and the second memory cell has a second voltage. Some embodiments include erase verifying only the first memory cell and second memory cell in a first erase verify operation, and erase verifying the plurality of intermediate memory cells in a second erase verify operation. Other embodiments including additional apparatus, systems, and methods are disclosed.

摘要翻译： 各种实施例包括擦除存储器件的一串存储器单元的至少一个存储单元，而存储器单元串的第一存储单元和第二存储单元中的至少一个的控制栅具有第一电压，而 第一存储单元与第二存储单元之间的多个中间存储单元的每个存储单元的控制栅极具有第二电压。 一些实施例包括在第一擦除验证操作中仅擦除第一存储器单元和第二存储器单元的擦除，以及在第二擦除验证操作中擦除验证多个中间存储器单元。 公开了包括附加装置，系统和方法的其它实施例。

公开(公告)号：US07539052B2

公开(公告)日：2009-05-26

申请号：US11646815

申请日：2006-12-28

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/12

摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for programming an array of non-volatile multilevel memory cells to a number of threshold voltage ranges. One method includes programming a lower page of a first wordline cell to increase a threshold voltage (Vt) of the first wordline cell to a first Vt within a lowermost Vt range. The method includes programming a lower page of a second wordline cell prior to programming an upper page of the first wordline cell. The method includes programming the upper page of the first wordline cell such that the first Vt is increased to a second Vt, wherein the second Vt is within a Vt range which is then a lowermost Vt range and is positive.

摘要翻译： 本公开的实施例提供用于将非易失性多电平存储器单元的阵列编程为多个阈值电压范围的方法，设备，模块和系统。 一种方法包括编程第一字线单元的下页以将第一字线单元的阈值电压（Vt）增加到最低Vt范围内的第一Vt。 该方法包括在编程第一字线单元的上部页之前对第二字线单元的下部页进行编程。 所述方法包括对所述第一字线单元的上部页进行编程，使得所述第一Vt增加到第二Vt，其中所述第二Vt在Vt范围内，其为最低Vt范围并且为正。

公开(公告)号：US20090113259A1

公开(公告)日：2009-04-30

申请号：US11926713

申请日：2007-10-29

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： G11C29/00

CPC分类号： G11C16/28 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/3445 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50 ,  G11C29/52

摘要： Embodiments of the present disclosure provide methods, devices, and systems for performing a programming operation on an array of non-volatile memory cells. One method includes programming a number of cells to a number of final data states. The method includes performing, prior to completion of, e.g., finishing, the programming operation, an erase state check on a subset of the number of cells, which were to be programmed to an erased state.

摘要翻译： 本公开的实施例提供了用于在非易失性存储器单元阵列上执行编程操作的方法，装置和系统。 一种方法包括将多个单元编程到多个最终数据状态。 该方法包括在完成例如完成编程操作之前，对要被编程为擦除状态的单元数目的子集执行擦除状态检查。

公开(公告)号：US20090086539A1

公开(公告)日：2009-04-02

申请号：US12329932

申请日：2008-12-08

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C5/04 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/5641

摘要： Memory arrays, and modules, devices and systems that utilize such memory arrays, are described as having a single level non-volatile memory cell interposed between and coupled to a select gate and a multiple level non-volatile memory cell. Various embodiments include structure, process, and operation and their applicability for memory devices and systems. In some embodiments, a memory array is described as including a number of select gates coupled in series to a number of single level non-volatile memory cells and a number of multiple level non-volatile memory cells, where a first select gate is coupled to a first single level non-volatile memory cell interposed between and coupled to the first select gate and a first multiple level non-volatile memory cell.

摘要翻译： 使用这种存储器阵列的存储器阵列和模块，设备和系统被描述为具有插入在选择栅极和多级非易失性存储器单元之间并耦合到选择栅极和多级非易失性存储器单元的单级非易失性存储器单元。 各种实施例包括结构，过程和操作及其对存储器件和系统的适用性。 在一些实施例中，存储器阵列被描述为包括与多个单级非易失性存储器单元和多个等级非易失性存储器单元串联耦合的多个选择栅极，其中第一选择栅极耦合到 插入在第一选择栅极之间并耦合到第一选择栅极和第一多级非易失性存储器单元的第一单级非易失性存储器单元。

公开(公告)号：US20090068812A1

公开(公告)日：2009-03-12

申请号：US12271132

申请日：2008-11-14

申请人： Kirk Prall ,  Behnam Moradi ,  Seiichi Aritome ,  Di Li ,  Chris Larsen

发明人： Kirk Prall ,  Behnam Moradi ,  Seiichi Aritome ,  Di Li ,  Chris Larsen

IPC分类号： H01L21/336

CPC分类号： H01L29/66825 ,  H01L21/22 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/324 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/788

摘要： Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.

摘要翻译： 公开了一种使用卤素离子注入和扩散工艺形成存储器件的方法。 在一个说明性实施例中，该方法包括在半导体衬底上形成多个字线结构，每个字线结构包括栅极绝缘层，执行LDD离子注入工艺，以在字线之间的衬底中形成LDD掺杂区域 结构，执行卤素离子注入工艺，以将卤素原子植入到半导体衬底中的字线结构之间，以及执行至少一个退火工艺，以使至少一些卤素原子扩散到相邻字的栅极绝缘层中 线结构。

公开(公告)号：US07440321B2

公开(公告)日：2008-10-21

申请号：US11402535

申请日：2006-04-12

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/12 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A portion of a memory array has a string of two or more non-volatile memory cells, a first select gate coupled in series with one non-volatile memory cell of the string of two or more non-volatile memory cells, and a second select gate coupled in series with the first select gate. A length of the second select gate is greater than a length of the first select gate.

摘要翻译： 存储器阵列的一部分具有两个或更多个非易失性存储器单元的串，第一选择栅极与两个或更多个非易失性存储器单元的串的一个非易失性存储器单元串联耦合，并且第二选择 栅极与第一选择栅极串联耦合。 第二选择栅极的长度大于第一选择栅极的长度。