Semiconductor device, and method of fabricating the same
    101.
    发明授权
    Semiconductor device, and method of fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号:US07482627B2

    公开(公告)日:2009-01-27

    申请号:US10337725

    申请日:2003-01-08

    IPC分类号: H01L29/04

    CPC分类号: H01L27/12 H01L27/1281

    摘要: A crystalline semiconductor film in which the locations and sizes of crystal grains have been controlled, is prepared, and a TFT capable of high speed operation is realized by employing the crystalline semiconductor film as the channel forming region of the TFT. An organic resin film (2 in FIG. 1) having a predetermined shape is provided on a substrate (1), whereupon an inorganic insulating film (3) and an amorphous semiconductor film are formed. Subsequently, the amorphous semiconductor film is crystallized by laser annealing. The material and thickness of the organic resin film (2) in the predetermined shape or those of the inorganic insulating film (3) are properly regulated, whereby the cooling rate of the semiconductor film is lowered to form a first region (4a) in which crystal grain diameters are large.

    摘要翻译: 准备晶体半导体膜,其中晶体的位置和尺寸已经被控制,并且通过使用晶体半导体膜作为TFT的沟道形成区域来实现能够高速操作的TFT。 在基板(1)上设置具有规定形状的有机树脂膜(图1中的2),形成无机绝缘膜(3)和非晶半导体膜。 随后,通过激光退火使非晶半导体膜结晶。 对规定形状的有机树脂膜(2)的材料和厚度进行适当的调整,半导体膜的冷却速度降低,形成第一区域(4a) 晶粒直径大。

    Colpitts oscillator
    102.
    发明授权
    Colpitts oscillator 失效
    Colpitts振荡器

    公开(公告)号:US07369005B2

    公开(公告)日:2008-05-06

    申请号:US11447190

    申请日:2006-06-05

    申请人: Kenji Kasahara

    发明人: Kenji Kasahara

    IPC分类号: H03B5/32

    摘要: Oscillation in which unwanted vibration (B mode) is surely suppressed while stable oscillation by principal vibration (C mode) is obtained is obtained. In a Colpitts oscillator including a piezoelectric vibrator, a transistor, and a first and second divided capacitive components, by inserting a feedback circuit formed by connecting a third capacitive component and a first inductor in series between a connection midpoint between the first capacitive component and the second capacitive component and an emitter of the transistor, inserting a second inductor in parallel with the second capacitive component, and setting the parallel resonance frequency of the second capacitive component and the second inductor in the vicinity of the oscillation frequency of the oscillator, the frequency band in which the negative resistance of the circuit side seen from the piezoelectric vibrator appears is set to a narrow band containing only a desired frequency to suppress unwanted vibration of the oscillator.

    摘要翻译: 获得了通过主振动(C模式)稳定振荡时可靠地抑制不希望的振动(B模式)的振荡。 在包括压电振动器,晶体管以及第一和第二分开的电容性部件的Colpitts振荡器中,通过插入通过将第三电容部件和第一电感器串联连接而形成的反馈电路,所述第三电容部件和第一电感器串联连接在第一电容部件和 所述晶体管的第二电容分量和发射极插入与所述第二电容分量并联的第二电感,并且将所述第二电容分量和所述第二电感器的并联谐振频率设置在所述振荡器的振荡频率附近,所述频率 出现从压电振动器看到的电路侧的负电阻的频带被设置为仅包含期望频率的窄带,以抑制振荡器的不期望的振动。

    Piezooscillator
    104.
    发明授权
    Piezooscillator 失效
    压电器

    公开(公告)号:US07304413B2

    公开(公告)日:2007-12-04

    申请号:US11501133

    申请日:2006-08-08

    申请人: Kenji Kasahara

    发明人: Kenji Kasahara

    IPC分类号: H01L41/053

    摘要: A piezooscillator having a piezoelectric resonator, composed of: a case surrounding a space where the piezoelectric resonator is provided and including a substrate and a cover; a buffer material supporting the piezoelectric resonator and suppressing a shock conveyed from the case to the piezoelectric resonator; and a wiring member electrically connecting the piezoelectric resonator and the substrate and having flexibility, or composed of: a case surrounding a space where the piezoelectric resonator is provided and including a first substrate and a cover; a second substrate mounting the piezoelectric resonator thereon; a buffer material supporting the second substrate and suppressing a shock conveyed from the case to the piezoelectric resonator; and a wiring member electrically connecting the first and second substrates and having flexibility, in which, when the case suffers the shock from outside, the buffer material absorbs the shock to prevent the shock conveyance to the piezoelectric resonator and frequency variation arising in the piezooscillator, realizing shock-resistance improvement, is provided.

    摘要翻译: 一种具有压电谐振器的压电振荡器,包括:围绕设置压电谐振器的空间的壳体,包括基板和盖; 支撑所述压电谐振器并且抑制从所述壳体传送到所述压电谐振器的冲击的缓冲材料; 以及布线构件,其电连接所述压电谐振器和所述基板并具有柔性,或者由围绕设置所述压电谐振器的空间的壳体构成,并且包括第一基板和盖; 在其上安装压电谐振器的第二衬底; 支撑所述第二基板并且抑制从所述壳体传送到所述压电谐振器的冲击的缓冲材料; 以及电连接第一和第二基板并具有柔性的布线构件,其中当外壳受到来自外部的冲击时,缓冲材料吸收冲击以防止压电谐振器的冲击输送和压电振荡器中产生的频率变化, 实现抗冲击性提高。

    Semiconductor device and method of manufacturing the same
    106.
    发明申请
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号:US20070196960A1

    公开(公告)日:2007-08-23

    申请号:US11785633

    申请日:2007-04-19

    IPC分类号: H01L21/70

    摘要: The lip-type seal of the present invention is a lip-type seal with which the outer periphery of a rotational shaft (S) supported by a predetermined housing (H) is sealed. The lip-type seal is made up of a first annular reinforcing member (11) and a first sealing member (12). The first reinforcing member (11) includes a wall surface part (11a) defining a hole through which the rotational shaft (S) is passed and a cylindrical part (11b) bent from the outer edge of the wall surface part (11a). The first sealing member (12) includes an annular base (12a) that is joined to the housing (H), a first lip part (12b) that extends almost conically from the base (12a) inwardly in the radial direction and that comes into contact with the rotational shaft (S), and an annular concave part (12c) formed in the base (12a) so as to detachably fit the cylindrical part (11b). Accordingly, a desired sealing capability can be secured, and the components can be easily assembled, disassembled, and recycled.

    摘要翻译: 本发明的唇形密封件是密封由预定壳体(H)支撑的旋转轴(S)的外周的唇型密封件。 唇形密封件由第一环形加强件(11)和第一密封件(12)构成。 第一加强构件(11)包括限定旋转轴(S)穿过的孔的壁表面部分(11a)和从壁表面部分(11a)的外边缘弯曲的圆柱形部分(11b) )。 第一密封构件(12)包括连接到壳体(H)的环形基部(12a),从基部(12a)沿径向向内向内延伸几乎三角形的第一唇部(12b) 与所述旋转轴(S)接触的环形凹部(12c)和形成在所述基部(12a)中的环状凹部(12c),以便可拆卸地配合所述圆筒部(11b)。 因此,可以确保期望的密封能力,并且可以容易地组装,拆卸和再循环部件。

    Semiconductor device with enhanced orientation ratio and method of manufacturing same
    108.
    发明授权
    Semiconductor device with enhanced orientation ratio and method of manufacturing same 有权
    具有增强取向比的半导体器件及其制造方法

    公开(公告)号:US07196400B2

    公开(公告)日:2007-03-27

    申请号:US10835077

    申请日:2004-04-30

    摘要: An object is to enhance the orientation ratio of a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film while using as a substrate a less-heat-resistive material such as glass thereby providing a semiconductor device using a crystalline semiconductor film with high quality equivalent to a single crystal. A first crystalline semiconductor film and a second crystalline semiconductor film are formed overlying a substrate, which integrally structure a crystalline semiconductor layer. The first and second crystalline semiconductor films are polycrystalline bodies aggregated with a plurality of crystal grains. However, the crystal grains are aligned toward a (101)-plane orientation at a ratio of 30 percent or greater, preferably 80 percent or greater. Also, relying on a plane orientation of the crystal grains in the first crystalline semiconductor film, the second crystalline semiconductor film has a plane orientation also aligned in the same direction with a probability of 60 percent or higher.

    摘要翻译: 目的是提高通过使非晶半导体膜结晶而获得的结晶半导体膜的取向比,同时使用诸如玻璃之类的耐热性较差的材料作为基底,从而提供使用高质量的晶体半导体膜的半导体器件,相当于 单晶。 第一晶体半导体膜和第二晶体半导体膜形成在基板上,其一体地结构化结晶半导体层。 第一和第二晶体半导体膜是与多个晶粒聚集的多晶体。 然而,晶粒以30%或更大,优选80%或更大的比例朝向(101)面平面取向。 此外,依靠第一结晶半导体膜中的晶粒的平面取向,第二结晶半导体膜的面取向也以相同方向排列,概率为60%以上。

    Semiconductor apparatus having semiconductor circuits made of semiconductor devices, and method of manufacture thereof
    109.
    发明申请
    Semiconductor apparatus having semiconductor circuits made of semiconductor devices, and method of manufacture thereof 审中-公开
    具有半导体装置的半导体电路的半导体装置及其制造方法

    公开(公告)号:US20070063199A1

    公开(公告)日:2007-03-22

    申请号:US11600064

    申请日:2006-11-16

    申请人: Kenji Kasahara

    发明人: Kenji Kasahara

    IPC分类号: H01L29/04

    摘要: A semiconductor device comprises a first insulating film provided over a substrate and heat-treated, a second insulating film provided over the first insulating film, and a semiconductor film provided over the second insulating film, the second insulating film and the semiconductor film being formed successively without exposing them to the atmosphere.

    摘要翻译: 半导体器件包括:设置在基板上并进行热处理的第一绝缘膜,设置在第一绝缘膜上的第二绝缘膜;以及设置在第二绝缘膜上的半导体膜,第二绝缘膜和半导体膜,依次形成 而不会让他们暴露在大气中。

    Semiconductor device and manufacturing method thereof
    110.
    发明授权
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号:US07176068B2

    公开(公告)日:2007-02-13

    申请号:US10756455

    申请日:2004-01-14

    IPC分类号: H01L21/00

    摘要: The present invention provides a semiconductor device in which a bottom-gate TFT or an inverted stagger TFT arranged in each circuit is suitably constructed in conformity with the functionality of the respective circuits, thereby attaining an improvement in the operating efficiency and reliability of the semiconductor device. In the structure, LDD regions in a pixel TFT are arranged so as not to overlap with a channel protection insulating film and to overlap with a gate electrode by at least a portion thereof. LDD regions in an N-channel TFT of a drive circuit is arranged so as not to overlap with a channel protection insulating film and to overlap with a gate electrode by at least a portion thereof. LDD regions in a P-channel TFT of the drive circuit is arranged so as to overlap with a channel protection insulating film and to overlap with the gate electrode.

    摘要翻译: 本发明提供了一种半导体器件,其中布置在每个电路中的底栅TFT或反向交错TFT适当地构成为与各个电路的功能一致,从而提高了半导体器件的工作效率和可靠性 。 在该结构中,像素TFT中的LDD区域布置成不与沟道保护绝缘膜重叠,并且通过其至少一部分与栅电极重叠。 驱动电路的N沟道TFT中的LDD区域布置成不与沟道保护绝缘膜重叠,并且通过其至少一部分与栅电极重叠。 驱动电路的P沟道TFT中的LDD区域布置成与沟道保护绝缘膜重叠并与栅电极重叠。