公开(公告)号：US08629008B2

公开(公告)日：2014-01-14

申请号：US13348018

申请日：2012-01-11

申请人： Balasubramanian S. Haran ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth

发明人： Balasubramanian S. Haran ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth

IPC分类号： H01L21/02

CPC分类号： H01L29/0653 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78654

摘要： After formation of raised source and drain regions, a conformal dielectric material liner is deposited within recessed regions formed by removal of shallow trench isolation structures and underlying portions of a buried insulator layer in a semiconductor-on-insulator (SOI) substrate. A dielectric material that is different from the material of the conformal dielectric material liner is subsequently deposited and planarized to form a planarized dielectric material layer. The planarized dielectric material layer is recessed selective to the conformal dielectric material liner to form dielectric fill portions that fill the recessed regions. Horizontal portions of the conformal dielectric material liner are removed by an anisotropic etch, while remaining portions of the conformal dielectric material liner form an outer gate spacer. At least one contact-level dielectric layer is deposited. Contact via structures electrically isolated from a handle substrate can be formed within the contact via holes.

摘要翻译： 在形成升高的源极和漏极区域之后，通过去除绝缘体上半导体（SOI）衬底中的浅沟槽隔离结构和掩埋绝缘体层的下面部分而形成的凹陷区域内淀积保形电介质材料衬垫。 随后沉积并平面化与保形介质材料衬垫的材料不同的介电材料，以形成平坦化的介电材料层。 平坦化的介电材料层对保形介电材料衬垫有选择性的凹陷，以形成填充凹陷区域的介电填充部分。 通过各向异性蚀刻去除保形电介质材料衬里的水平部分，而保形介质材料衬垫的剩余部分形成外栅间隔件。 沉积至少一个接触电介质层。 可以在接触通孔内形成与手柄基板电隔离的结构的接触。

公开(公告)号：US20130181261A1

公开(公告)日：2013-07-18

申请号：US13348894

申请日：2012-01-12

申请人： VEERARAGHAVAN S. BASKER ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

发明人： VEERARAGHAVAN S. BASKER ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/20

CPC分类号： H01L29/66545 ,  H01L21/76897 ,  H01L29/66628 ,  H01L29/78

摘要： A borderless contact structure or partially borderless contact structure and methods of manufacture are disclosed. The method includes forming a gate structure and a space within the gate structure, defined by spacers. The method further includes blanket depositing a sealing material in the space, over the gate structure and on a semiconductor material. The method further includes removing the sealing material from over the gate structure and on the semiconductor material, leaving the sealing material within the space. The method further includes forming an interlevel dielectric material over the gate structure. The method further includes patterning the interlevel dielectric material to form an opening exposing the semiconductor material and a portion of the gate structure. The method further includes forming a contact in the opening formed in the interlevel dielectric material.

摘要翻译： 公开了无边界接触结构或部分无边界接触结构和制造方法。 该方法包括在栅极结构内形成栅极结构和由间隔物限定的空间。 该方法还包括在该空间中，在栅极结构上和半导体材料上覆盖密封材料。 该方法还包括从栅极结构和半导体材料上方移除密封材料，将密封材料留在空间内。 该方法还包括在栅极结构上形成层间电介质材料。 该方法进一步包括图案化层间电介质材料以形成暴露半导体材料和栅极结构的一部分的开口。 该方法还包括在形成在层间电介质材料中的开口中形成接触。

公开(公告)号：US20130175622A1

公开(公告)日：2013-07-11

申请号：US13348018

申请日：2012-01-11

申请人： Balasubramanian S. Haran ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth

发明人： Balasubramanian S. Haran ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0653 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78654

摘要： After formation of raised source and drain regions, a conformal dielectric material liner is deposited within recessed regions formed by removal of shallow trench isolation structures and underlying portions of a buried insulator layer in a semiconductor-on-insulator (SOI) substrate. A dielectric material that is different from the material of the conformal dielectric material liner is subsequently deposited and planarized to form a planarized dielectric material layer. The planarized dielectric material layer is recessed selective to the conformal dielectric material liner to form dielectric fill portions that fill the recessed regions. Horizontal portions of the conformal dielectric material liner are removed by an anisotropic etch, while remaining portions of the conformal dielectric material liner form an outer gate spacer. At least one contact-level dielectric layer is deposited. Contact via structures electrically isolated from a handle substrate can be formed within the contact via holes.

摘要翻译： 在形成升高的源极和漏极区域之后，通过去除绝缘体上半导体（SOI）衬底中的浅沟槽隔离结构和掩埋绝缘体层的下面部分而形成的凹陷区域内淀积保形电介质材料衬垫。 随后沉积并平面化与保形介质材料衬垫的材料不同的介电材料，以形成平坦化的介电材料层。 平坦化的介电材料层对保形介电材料衬垫有选择性的凹陷，以形成填充凹陷区域的介电填充部分。 通过各向异性蚀刻去除保形电介质材料衬里的水平部分，而保形介质材料衬垫的剩余部分形成外栅间隔件。 沉积至少一个接触电介质层。 可以在接触通孔内形成与手柄基板电隔离的结构的接触。

公开(公告)号：US08349674B2

公开(公告)日：2013-01-08

申请号：US13073151

申请日：2011-03-28

申请人： Shom Ponoth ,  David V. Horak ,  Charles W. Koburger, III ,  Chih-Chao Yang

发明人： Shom Ponoth ,  David V. Horak ,  Charles W. Koburger, III ,  Chih-Chao Yang

IPC分类号： H01L21/338

CPC分类号： H01L29/66545 ,  H01L21/76897 ,  H01L29/41733 ,  H01L29/41783 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66553

摘要： Embodiments of the present invention provide a method of forming a semiconductor structure. The method includes creating an opening inside a dielectric layer, the dielectric layer being formed on top of a substrate and the opening exposing a channel region of a transistor in the substrate; depositing a work-function layer lining the opening and covering the channel region; forming a gate conductor covering a first portion of the work-function layer, the first portion of the work-function layer being on top of the channel region; and removing a second portion of the work-function layer, the second portion of the work-function layer surrounding the first portion of the work-function layer, wherein the removal of the second portion of the work-function layer insulates the first portion of the work-function layer from rest of the work-function layer.

摘要翻译： 本发明的实施例提供了形成半导体结构的方法。 该方法包括在电介质层内形成开口，介电层形成在衬底的顶部，并且该开口暴露衬底中晶体管的沟道区; 沉积衬套开口并覆盖通道区域的功函数层; 形成覆盖所述功函数层的第一部分的栅极导体，所述功函数层的所述第一部分位于所述沟道区的顶部; 并且去除所述功函数层的第二部分，所述功函数层的包围所述功函数层的第一部分的所述第二部分，其中所述功函数层的所述第二部分的去除使所述功函数层的第一部分绝缘 工作功能层的工作功能层。

公开(公告)号：US20120329275A1

公开(公告)日：2012-12-27

申请号：US13607677

申请日：2012-09-08

申请人： Shom Ponoth ,  David V. Horak ,  Charles W. Koburger, III ,  Chih-Chao Yang

发明人： Shom Ponoth ,  David V. Horak ,  Charles W. Koburger, III ,  Chih-Chao Yang

IPC分类号： H01L21/768

CPC分类号： H01L23/528 ,  H01L21/76885 ,  H01L21/76897 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A metal layer is deposited on a planar surface on which top surfaces of underlying metal vias are exposed. The metal layer is patterned to form at least one metal block, which has a horizontal cross-sectional area of a metal line to be formed and at least one overlying metal via to be formed. Each upper portion of underlying metal vias is recessed outside of the area of a metal block located directly above. The upper portion of the at least one metal block is lithographically patterned to form an integrated line and via structure including a metal line having a substantially constant width and at least one overlying metal via having the same substantially constant width and borderlessly aligned to the metal line. An overlying-level dielectric material layer is deposited and planarized so that top surface(s) of the at least one overlying metal via is/are exposed.

公开(公告)号：US20120248508A1

公开(公告)日：2012-10-04

申请号：US13073151

申请日：2011-03-28

申请人： Shom Ponoth ,  David V. Horak ,  Charles W. Koburger, III ,  Chih-Chao Yang

发明人： Shom Ponoth ,  David V. Horak ,  Charles W. Koburger, III ,  Chih-Chao Yang

IPC分类号： H01L29/772 ,  H01L21/28

CPC分类号： H01L29/66545 ,  H01L21/76897 ,  H01L29/41733 ,  H01L29/41783 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66553

摘要： Embodiments of the present invention provide a method of forming a semiconductor structure. The method includes creating an opening inside a dielectric layer, the dielectric layer being formed on top of a substrate and the opening exposing a channel region of a transistor in the substrate; depositing a work-function layer lining the opening and covering the channel region; forming a gate conductor covering a first portion of the work-function layer, the first portion of the work-function layer being on top of the channel region; and removing a second portion of the work-function layer, the second portion of the work-function layer surrounding the first portion of the work-function layer, wherein the removal of the second portion of the work-function layer insulates the first portion of the work-function layer from rest of the work-function layer.

摘要翻译： 本发明的实施例提供一种形成半导体结构的方法。 该方法包括在电介质层内形成开口，介电层形成在衬底的顶部，并且该开口暴露衬底中晶体管的沟道区; 沉积衬套开口并覆盖通道区域的功函数层; 形成覆盖所述功函数层的第一部分的栅极导体，所述功函数层的所述第一部分位于所述沟道区的顶部; 并且去除所述功函数层的第二部分，所述功函数层的包围所述功函数层的第一部分的所述第二部分，其中所述功函数层的所述第二部分的去除使所述功函数层的第一部分绝缘 工作功能层的工作功能层。

公开(公告)号：US20120187566A1

公开(公告)日：2012-07-26

申请号：US13013108

申请日：2011-01-25

申请人： David V. Horak ,  Elbert Huang ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

发明人： David V. Horak ,  Elbert Huang ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L23/522 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure is disclosed whereby multiple interconnect layers having effective air gaps positioned in regions most susceptible to capacitive coupling can be formed. The method includes providing a layer of conductive features, the layer including at least two line members disposed on a substrate and spaced from one another by less than or equal to an effective distance, and at least one such line member also having a via member extending away from the substrate, depositing a poorly conformal dielectric coating to form an air gap between such line members, and exposing a top end of the via.

摘要翻译： 公开了一种方法和结构，其中可以形成具有位于最容易受电容耦合的区域中的有效气隙的多个互连层。 该方法包括提供导电特征层，所述层包括设置在基底上并彼此隔开小于或等于有效距离的至少两个线构件，以及至少一个这样的线构件，其还具有延伸的通孔构件 离开基板，沉积不良共形介电涂层以在这些线构件之间形成气隙，并露出通孔的顶端。

公开(公告)号：US20120086128A1

公开(公告)日：2012-04-12

申请号：US12899911

申请日：2010-10-07

申请人： Shom Ponoth ,  David V. Horak ,  Charles W. Koburger, III ,  Chih-Chao Yang

发明人： Shom Ponoth ,  David V. Horak ,  Charles W. Koburger, III ,  Chih-Chao Yang

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/528 ,  H01L21/76885 ,  H01L21/76897 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A metal layer is deposited on a planar surface on which top surfaces of underlying metal vias are exposed. The metal layer is patterned to form at least one metal block, which has a horizontal cross-sectional area of a metal line to be formed and at least one overlying metal via to be formed. Each upper portion of underlying metal vias is recessed outside of the area of a metal block located directly above. The upper portion of the at least one metal block is lithographically patterned to form an integrated line and via structure including a metal line having a substantially constant width and at least one overlying metal via having the same substantially constant width and borderlessly aligned to the metal line. An overlying-level dielectric material layer is deposited and planarized so that top surface(s) of the at least one overlying metal via is/are exposed.

摘要翻译： 金属层沉积在其上暴露下面的金属通孔的顶表面的平坦表面上。 图案化金属层以形成至少一个金属块，其具有要形成的金属线的水平横截面积和要形成的至少一个上覆的金属通孔。 下面的金属通孔的每个上部凹陷在位于正上方的金属块的区域的外部。 至少一个金属块的上部被光刻地图案化以形成集成线和通孔结构，其包括具有基本上恒定的宽度的金属线和至少一个覆盖的金属通孔，其具有相同的基本上恒定的宽度并且与金属线无边界地对准 。 沉积和平坦化上层电介质材料层，使得至少一个上覆金属通孔的顶表面被暴露。

公开(公告)号：US08877615B2

公开(公告)日：2014-11-04

申请号：US13431770

申请日：2012-03-27

申请人： Veeraraghavan S. Basker ,  David V. Horak ,  Hemanth Jagannathan ,  Charles W. Koburger, III

发明人： Veeraraghavan S. Basker ,  David V. Horak ,  Hemanth Jagannathan ,  Charles W. Koburger, III

IPC分类号： H01L21/20 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/78

CPC分类号： H01L29/785 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7845

摘要： A finFET structure and method of manufacture such structure is provided with lowered Ceff and enhanced stress. The finFET structure includes a plurality of finFET structures and a stress material forming part of a gate stack and in a space between adjacent ones of the plurality of finFET structures.

摘要翻译： FinFET结构及其制造方法具有降低的Ceff和增强的应力。 finFET结构包括多个finFET结构和形成栅极堆叠的一部分的应力材料，并且在多个finFET结构中的相邻空间之间的空间中。

公开(公告)号：US08765585B2

公开(公告)日：2014-07-01

申请号：US13095955

申请日：2011-04-28

申请人： Su C. Fan ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

发明人： Su C. Fan ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L21/311 ,  H01L21/336

CPC分类号： H01L29/78 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41775 ,  H01L29/66545

摘要： Each gate structure formed on the substrate includes a gate dielectric, a gate conductor, a first etch stop layer, and a gate cap dielectric. A second etch stop layer is formed over the gate structures, gate spacers, and source and drain regions. A first contact-level dielectric layer and a second contact-level dielectric layer are formed over the second etch stop layer. Gate contact via holes extending at least to the top surface of the gate cap dielectrics are formed. Source/drain contact via holes extending to the interface between the first and second contact-level dielectric layers are subsequently formed. The various contact via holes are vertically extended by simultaneously etching exposed gate cap dielectrics and exposed portions of the first contact-level dielectric layer, then by simultaneously etching the first and second etch stop layers. Source/drain contact vias self-aligned to the outer surfaces gate spacers are thereby formed.

摘要翻译： 形成在衬底上的每个栅极结构包括栅极电介质，栅极导体，第一蚀刻停止层和栅极盖电介质。 在栅极结构，栅极间隔物以及源极和漏极区域上形成第二蚀刻停止层。 在第二蚀刻停止层上方形成第一接触电介质层和第二接触电介质层。 形成至少延伸到栅极盖电介质的顶表面的栅极接触通孔。 随后形成延伸到第一和第二接触电介质层之间的界面的源极/漏极接触孔。 通过同时蚀刻暴露的栅极帽电介质和第一接触电介质层的暴露部分，然后同时蚀刻第一和第二蚀刻停止层，使各种接触通孔垂直延伸。 从而形成与外表面自对准的源极/漏极接触孔。