公开(公告)号：US5627987A

公开(公告)日：1997-05-06

申请号：US21098

申请日：1993-02-23

申请人： Hiroshi Nozue ,  Mitsuo Saito ,  Kenichi Maeda ,  Shigehiro Asano ,  Toshio Okamoto ,  Shin Sungho ,  Hideo Segawa

发明人： Hiroshi Nozue ,  Mitsuo Saito ,  Kenichi Maeda ,  Shigehiro Asano ,  Toshio Okamoto ,  Shin Sungho ,  Hideo Segawa

IPC分类号： G06F12/10 ,  G06F12/14 ,  G06F12/00

CPC分类号： G06F12/1458 ,  G06F12/109 ,  G06F12/1483 ,  G06F12/1491 ,  G06F2212/656

摘要： A memory management and protection system for realizing a high speed execution and a proper and flexible memory access control for multiple programs sharing an identical logical address space. In the system, the memory access is permitted according to a segment identifier identifying a segment in the logical address space, and a memory protection information for a region in each segment including a target right permission to indicate assigned rights to make a memory access from the region to each of the segments, and an execution permission to indicate a type of the memory access permitted by the right permission. Alternatively, a memory access can be permitted by using an access control list to be attached to each address table entry, which stores a plurality of program numbers identifying programs which are permitted to make accesses to the logical address stored in each address table entry, among which one that matches with the current program number is to be searched. Also, it is preferable to allocate a plurality of programs within a limit of available memory protection capacity to an identical logical address space, without any overlap between adjacently allocated address regions.

摘要翻译： 一种用于实现高速执行的存储器管理和保护系统，以及用于共享相同逻辑地址空间的多个程序的适当且灵活的存储器访问控制。 在系统中，根据标识逻辑地址空间中的段的段标识符，允许存储器访问，以及每个区段中的区域的存储器保护信息，包括目标权限，以指示从存储器访问的指定的权限 区域，以及用于指示由权限许可允许的存储器访问的类型的执行许可。 或者，可以通过使用附加到每个地址表条目的访问控制列表来允许存储器访问，每个地址表条目存储多个程序号，标识被允许访问存储在每个地址表条目中的逻辑地址的程序， 将搜索与当前节目号匹配的那个。 此外，优选地，在可用存储器保护容量的限制内将多个程序分配给相同的逻辑地址空间，而不会在相邻分配的地址区域之间发生任何重叠。

公开(公告)号：US08719615B2

公开(公告)日：2014-05-06

申请号：US13064316

申请日：2011-03-17

申请人： Yohei Hasegawa ,  Yutaka Yamada ,  Takashi Yoshikawa ,  Shigehiro Asano

发明人： Yohei Hasegawa ,  Yutaka Yamada ,  Takashi Yoshikawa ,  Shigehiro Asano

IPC分类号： G06F1/12

CPC分类号： G06F1/12 ,  G06F9/3887 ,  G06F9/3893

摘要： A semiconductor device performs operation in synchronization with a certain clock signal. The semiconductor device includes a control unit for outputting operation control information, a storage unit for storing data, a first operation unit for performing operation on first data in accordance with first operation control information, and a second operation unit for performing operation on second data in accordance with second operation control information. The first operation unit includes a plurality of operation circuits. The number of logic gates constituting the entire operation circuits is m. The second operation unit includes at least one operation circuit in which the number of logic gates is n (n>m). Each of the total delay of the operation unit or the total delay of the operation unit is set at a value equal to or less than the cycle of the clock signal.

摘要翻译： 半导体器件与某个时钟信号同步地进行操作。 该半导体装置包括用于输出操作控制信息的控制单元，用于存储数据的存储单元，用于根据第一操作控制信息对第一数据执行操作的第一操作单元和用于对第二数据执行操作的第二操作单元 根据第二操作控制信息。 第一操作单元包括多个操作电路。 构成整个运算电路的逻辑门的数量为m。 第二操作单元包括其中逻辑门数为n（n> m）的至少一个操作电路。 操作单元的总延迟或操作单元的总延迟中的每一个被设置为等于或小于时钟信号的周期的值。

公开(公告)号：US08611368B2

公开(公告)日：2013-12-17

申请号：US13162917

申请日：2011-06-17

申请人： Shigehiro Asano ,  Charles Ray Johns ,  Matthew Edward King ,  Peichun Peter Liu ,  David Mui ,  Jieming Qi

发明人： Shigehiro Asano ,  Charles Ray Johns ,  Matthew Edward King ,  Peichun Peter Liu ,  David Mui ,  Jieming Qi

IPC分类号： H04L12/43 ,  H04L12/28

CPC分类号： H04L41/0896

摘要： Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology.

公开(公告)号：US08195975B2

公开(公告)日：2012-06-05

申请号：US12341147

申请日：2008-12-22

申请人： Yutaka Yamada ,  Takashi Yoshikawa ,  Shigehiro Asano

发明人： Yutaka Yamada ,  Takashi Yoshikawa ,  Shigehiro Asano

IPC分类号： G06F1/04

CPC分类号： G06F1/3203 ,  G06F1/3237 ,  G06F1/3287 ,  Y02D10/128 ,  Y02D10/171

摘要： A plurality of operation units connected in a pipeline structure performs an operation processing on data. A process control unit operates in synchronization with a system clock signal and generates a process control signal for controlling the operation units upon receiving a data notification signal that notifies the process control unit of an arrival of data from outside. A clock-control signal generating unit operates in synchronization with the system clock signal and generates a clock control signal for controlling a clock supply to each of the operation units upon receiving the process control signal.

摘要翻译： 连接在流水线结构中的多个操作单元对数据进行操作处理。 过程控制单元与系统时钟信号同步地操作，并且在接收到通知过程控制单元来自外部的数据到达的数据通知信号时产生用于控制操作单元的过程控制信号。 时钟控制信号产生单元与系统时钟信号同步地工作，并且在接收到处理控制信号时产生用于控制每个操作单元的时钟供给的时钟控制信号。

公开(公告)号：US07818546B2

公开(公告)日：2010-10-19

申请号：US11517327

申请日：2006-09-08

申请人： Shigehiro Asano ,  Takashi Yoshikawa

发明人： Shigehiro Asano ,  Takashi Yoshikawa

IPC分类号： G06F9/00 ,  G06F7/38 ,  G06F9/44 ,  G06F13/00

CPC分类号： G06F13/368

摘要： A bus apparatus for transferring information between a bus master and a bus slave includes a plurality of pipeline registers capable of transmitting information from the bus master to the bus slave by a pipeline processing; and a plurality of management devices that manage each pipeline register. Also, the management device includes: a holding state keeping unit that keeps a holding state as information indicating whether a current stage's pipeline register corresponding to the management device holds information; an adjacent stage's holding state specifying unit that specifies the holding state of a previous stage's pipeline register that transmits information to the current stage's pipeline register and the holding state of a subsequent stage's pipeline register to which information from the current stage's pipeline register is transmitted; and a transfer control unit that determines whether information held by the corresponding pipeline register is transferred.

摘要翻译： 用于在总线主机和总线从站之间传送信息的总线装置包括：能够通过流水线处理从总线主机向总线从机传输信息的多个流水线寄存器; 以及管理每个流水线寄存器的多个管理装置。 此外，管理装置包括：保持状态保持单元，其将保持状态保持为指示与管理装置对应的当前级的流水线寄存器是否保存信息的信息; 相邻级的保持状态指定单元，其指定向当前级的流水线寄存器发送信息的前一级的流水线寄存器的保持状态，以及发送来自当前级的流水线寄存器的信息的后级的流水线寄存器的保持状态; 以及传送控制单元，其确定由相应流水线寄存器保存的信息是否被传送。

公开(公告)号：US07720982B2

公开(公告)日：2010-05-18

申请号：US11716845

申请日：2007-03-12

申请人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  Charles Ray Johns ,  James Allan Kahle ,  Shigehiro Asano ,  Atsushi Kunimatsu

发明人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  Charles Ray Johns ,  James Allan Kahle ,  Shigehiro Asano ,  Atsushi Kunimatsu

IPC分类号： G06F15/16

CPC分类号： G06F9/4862 ,  G06F15/16 ,  H04L29/06027 ,  H04L63/168 ,  H04L67/10 ,  H04L67/34

摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.

摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。 统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。 每个软件单元在网络上唯一标识。 还提供了一种用于创建用于处理流数据的专用流水线的系统和方法。

公开(公告)号：US07653805B2

公开(公告)日：2010-01-26

申请号：US11727134

申请日：2007-03-23

申请人： Takashi Yoshikawa ,  Shigehiro Asano ,  Yutaka Yamada

发明人： Takashi Yoshikawa ,  Shigehiro Asano ,  Yutaka Yamada

IPC分类号： G06F15/76

CPC分类号： G06F15/7867

摘要： A semiconductor device for performing data processing by performing a plurality of computations in cycles includes a pipeline formed by connecting a plurality of computing units in series, each of the computing units including: a data line for receiving data; a control line for receiving a rule signal; a circuit information control unit configured to store, before data processing, several circuit information items, and to output a first one of the several circuit information items according to the rule signal received via the control line in a first cycle of the data processing; a processing element configured to construct an execution circuit according to the first circuit information item, to perform a computation using data from the data line, and to output a computation result; a data register for storing the computation result, and for outputting the computation result in a second cycle; and a control register for storing the rule signal and for outputting the rule signal in the second cycle. The semiconductor further includes a controller configured to control output timing of the rule signal to the control line of a first-stage one of the computing units in the pipeline and to control output timing of the data to the data line of the first-stage computing unit in the first cycle, so that the plurality of computing units are operated as a pipeline.

摘要翻译： 用于通过循环执行多个计算来执行数据处理的半导体装置包括通过串联连接多个计算单元而形成的流水线，每个计算单元包括：用于接收数据的数据线; 用于接收规则信号的控制线; 电路信息控制单元，被配置为在数据处理之前存储几个电路信息项，并且在数据处理的第一周期中根据经由控制线接收的规则信号来输出多个电路信息项中的第一个; 处理元件，被配置为构成根据第一电路信息项的执行电路，以使用来自数据线的数据执行计算，并输出计算结果; 数据寄存器，用于存储所述计算结果，并用于在第二周期中输出所述计算结果; 以及用于存储规则信号并在第二周期中输出规则信号的控制寄存器。 半导体还包括控制器，被配置为控制规则信号的输出定时到流水线中的计算单元的第一级的控制线，并且控制数据到第一级计算的数据线的输出定时 单元，使得多个计算单元作为流水线操作。

公开(公告)号：US20090327655A1

公开(公告)日：2009-12-31

申请号：US12372011

申请日：2009-02-17

申请人： Takashi Yoshikawa ,  Shigehiro Asano

发明人： Takashi Yoshikawa ,  Shigehiro Asano

IPC分类号： G06F15/76 ,  G06F15/00 ,  G06F9/44 ,  G06F9/30

CPC分类号： G06F9/3879 ,  G06F9/3897 ,  G06F15/7867 ,  Y02D10/12 ,  Y02D10/13

摘要： The semiconductor device includes a controller and a plurality of dynamically reconfigurable circuits connected to one another in series below the controller to perform operations in the manner of a pipeline. The controller inputs data and reconfiguration information to the first one of the dynamically reconfigurable circuits. Each of the dynamically reconfigurable circuits includes a processing unit that performs a data computation, an updating unit that updates the reconfiguration information, and a repetition controlling unit that determines whether to repeat the computation and controls the data and the reconfiguration information.

摘要翻译： 半导体器件包括控制器和多个在控制器下串联连接的可动态可重构电路，以以管道的方式执行操作。 控制器将数据和重配置信息输入到动态可重配置电路中的第一个。 每个动态可重配置电路包括执行数据计算的处理单元，更新重新配置信息的更新单元以及确定是否重复计算并控制数据和重新配置信息的重复控制单元。

公开(公告)号：US07613859B2

公开(公告)日：2009-11-03

申请号：US11853898

申请日：2007-09-12

申请人： Shigehiro Asano ,  Tsutomu Ishii

发明人： Shigehiro Asano ,  Tsutomu Ishii

IPC分类号： G06F13/00

CPC分类号： G06F13/368

摘要： Systems and methods for implementing back-off timing for retries of commands sent from a master device to a slave device over a split-transaction bus. One embodiment includes a buffer having entries for storing each pending command and associated information, including a number of retries of the command and a static pseudorandom timer expiration value. The timer expiration value of each entry is compared to a running counter according to a mask associated with the number of retries of the command corresponding to the entry. When the unmasked bits of the two values match, the command is retried. In one embodiment, the same portion of the buffer entry that is used to store the number of retries and the timer expiration value is alternately used to store a slave-generated tag that is received with an acknowledgment response.

摘要翻译： 用于通过分割事务总线实现从主设备发送到从设备的命令重试的退避时序的系统和方法。 一个实施例包括具有用于存储每个未决命令和相关信息的条目的缓冲器，包括命令的重试次数和静态伪随机定时器到期值。 根据与对应于条目的命令的重试次数相关联的掩码，将每个条目的定时器到期值与运行计数器进行比较。 当两个值的未屏蔽位匹配时，将重试该命令。 在一个实施例中，用于存储重试次数和定时器到期值的缓冲器条目的相同部分交替地用于存储用确认响应接收的从生产标签。

公开(公告)号：US07613841B2

公开(公告)日：2009-11-03

申请号：US11422646

申请日：2006-06-07

申请人： Shigehiro Asano ,  Thuong Truong

发明人： Shigehiro Asano ,  Thuong Truong

IPC分类号： G06F3/00

CPC分类号： G06F13/42

摘要： Systems and methods for enforcing in-order execution of commands sent from a master device to a slave device, where it is not necessary to provide a data buffer to store data associated with commands that are delayed to enforce in-order execution. In one embodiment, when a slave receives an execution synchronization command from a master, it determines whether its command queue contains unissued commands associated with master. If the command queue contains unissued commands, the slave issues a retry responsive to the execution synchronization command. If the command queue does not contain unissued commands, the slave issues an acknowledgment responsive to the execution synchronization command. The master will retry the execution synchronization command until the previous commands have been completed. Because the slave does not queue up any commands that would be delayed by the execution synchronization command, it does not have to provide space to store any associated data.

摘要翻译： 用于执行从主设备发送到从设备的命令的按顺序执行的系统和方法，其中不需要提供数据缓冲器来存储与被延迟以执行顺序执行的命令相关联的数据。 在一个实施例中，当从机从主机接收到执行同步命令时，它确定其命令队列是否包含与主机相关联的未发出的命令。 如果命令队列包含未发出的命令，则从站会根据执行同步命令发出重试。 如果命令队列不包含未发出的命令，则从机将响应于执行同步命令发出确认。 主机将重试执行同步命令，直到之前的命令完成。 因为从站不排队将被执行同步命令延迟的任何命令，所以它不必提供存储任何关联数据的空间。