公开(公告)号：US20230253460A1

公开(公告)日：2023-08-10

申请号：US18301146

申请日：2023-04-14

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Kevin Kyuheon CHO ,  Bongyong LEE ,  Kyeongseok PARK ,  Doojin CHOI ,  Thomas NEYER ,  Ki Min KIM

IPC分类号： H01L29/16 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/1608 ,  H01L29/1045 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/7802

摘要： A SiC MOSFET device with alternating p-well widths, including an undulating channel, is described. The undulating channel provides current paths of multiple widths, which enables optimization of on-resistance, transconductance, threshold voltage, and channel length. The multi-width p-well region further defines corresponding multi-width Junction FETs (JFETs). The multi-width JFETs enable improved response to a short-circuit event. A high breakdown voltage is obtained by distributing a high electric field in a JFET of a first width into a JFET of a second width.

公开(公告)号：US11715804B2

公开(公告)日：2023-08-01

申请号：US17450734

申请日：2021-10-13

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Andrei Konstantinov

IPC分类号： H01L29/872 ,  H01L29/16 ,  H01L29/06 ,  H01L29/66 ,  H01L21/04 ,  H01L29/36 ,  H01L29/04 ,  H01L21/761

CPC分类号： H01L29/872 ,  H01L21/046 ,  H01L21/047 ,  H01L21/0465 ,  H01L21/761 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/6606 ,  H01L29/045

摘要： A SiC Schottky rectifier with surge current ruggedness is described. The Schottky rectifier includes one or more multi-layer bodies that provide multiple types of surge current protection.

公开(公告)号：US11710687B2

公开(公告)日：2023-07-25

申请号：US16502441

申请日：2019-07-03

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Chee Hiong Chew ,  Yushuang Yao ,  Atapol Prajuckamol ,  Chuncao Niu

IPC分类号： H01L23/498 ,  H05K1/18 ,  H01L23/40 ,  H01L23/538 ,  H01L23/00

CPC分类号： H01L23/49811 ,  H01L23/40 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/562 ,  H05K1/184 ,  H01L2023/4087

摘要： A semiconductor guide pin is disclosed. Specific implementations may include a heatsink, one or more substrates coupled together, one or more pressfit pins coupled to the one or more substrates, and two or more guide pins coupled to the one or more substrates, where the two or more guide pins may have a height greater than the one or more pressfit pins.

公开(公告)号：US11710686B2

公开(公告)日：2023-07-25

申请号：US17457148

申请日：2021-12-01

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Stephen St. Germain ,  Jay A. Yoder ,  Dennis Lee Conner ,  Frank Robert Cervantes ,  Andrew Celaya

IPC分类号： H01L23/498 ,  H01L21/56 ,  H01L23/495 ,  H01L23/31

CPC分类号： H01L23/49805 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49811 ,  H01L23/49861 ,  H01L2924/0002 ,  H01L2924/181

摘要： Methods of forming semiconductor packages include providing a lead frame having leads and no tie-bars. Tape is attached to the lead frame and one or more semiconductor die are coupled therewith. Electrical contacts of the die are interconnected with the leads using electrical connectors. An encapsulated assembly is formed by at least partially encapsulating the die and electrical connectors. The assembly is singulated to form a semiconductor package. The tape is detached from the package or encapsulated assembly. One or more die attach flags may be attached to the tape and the die may be attached thereto. Semiconductor packages formed using the methods include one or more semiconductor die at least partially encapsulated, pins exposed through the encapsulant, electrical connectors within the encapsulant and electrically interconnecting the pins with electrical contacts of the die, and no tie-bars coupling the die with the pins. Packages may also include die attach flags.

公开(公告)号：US20230230895A1

公开(公告)日：2023-07-20

申请号：US18186842

申请日：2023-03-20

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Jerome TEYSSEYRE ,  Roveendra PAUL ,  Dukyong LEE

IPC分类号： H01L23/367 ,  H01L23/373 ,  H01L23/40

CPC分类号： H01L23/3675 ,  H01L23/3735 ,  H01L23/4006 ,  H01L2023/4087 ,  H01L2023/405 ,  H01L2023/4056 ,  H01L2023/4031

摘要： In one general aspect, an apparatus can include a first module including a first semiconductor die, and a first heatsink coupled to the first module where the first heatsink includes a substrate and a first plurality of protrusions. The apparatus can also include a second module including a second semiconductor die, and a second heatsink coupled to the second module and including a second plurality of protrusions. The apparatus can also include a cover defining a channel where the first plurality of protrusions of the first heatsink and the second plurality of protrusions of the second heatsink are disposed within the channel.

公开(公告)号：US11705901B2

公开(公告)日：2023-07-18

申请号：US17805916

申请日：2022-06-08

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Alexander Heubi

IPC分类号： H03K19/0185 ,  H03K17/16

CPC分类号： H03K17/161 ,  H03K19/018521

摘要： A driver circuit drives an output terminal with an input/output voltage using an NMOS transistor and a PMOS transistor. A pre-driver for the NMOS transistor supplied with a drive voltage and receives a data signal referenced to the drive voltage. A pre-driver for the PMOS transistor has a positive supply input connected to the positive supply rail, a negative supply input receiving a second drive voltage equal to the supply voltage minus the drive voltage. A level shifter circuit, shifts the data signal to be referenced between the supply voltage and the second drive voltage. A charge pump circuit for providing second drive voltage, the charge pump circuit driven with a variable switching frequency proportional to a current of the PMOS transistor.

公开(公告)号：US20230223850A1

公开(公告)日：2023-07-13

申请号：US17647631

申请日：2022-01-11

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Karel PTACEK ,  Roman STULER ,  Roman RADVAN

IPC分类号： H02M3/158 ,  H02M1/00 ,  H02M1/08 ,  H03K17/16

CPC分类号： H02M3/158 ,  H02M1/0029 ,  H02M1/0009 ,  H02M1/08 ,  H03K17/162 ,  H02M1/0025

摘要： Switching circuits, half-bridge power converters, and methods for operating a switching circuit including a switching transistor coupled to a load. The method includes applying, with a driver, a gate voltage to the switching transistor. The method also includes generating, with a feedback capacitor, a feedback current based on a change in a voltage sensed at a drain terminal of the switching transistor when the switching transistor turns on. The method further includes applying the feedback current to the driver to limit the gate voltage applied to the switching transistor. The method also includes adjusting, with a controller, a switching slew rate of the switching transistor by draining an amount of the feedback current.

公开(公告)号：US20230223474A1

公开(公告)日：2023-07-13

申请号：US18188233

申请日：2023-03-22

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Xiaoli WU ,  Joseph Andrew YEDINAK

IPC分类号： H01L29/10 ,  H01L29/40 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/1095 ,  H01L29/407 ,  H01L29/7803 ,  H01L29/7813 ,  H01L29/66734

摘要： A semiconductor device includes a region of semiconductor material of a first conductivity type. A body region of a second conductivity type is in the region of semiconductor material. The body region includes a first segment with a first peak dopant concentration, and a second segment laterally adjacent to the first segment with a second peak dopant concentration. A source region of the first conductivity type is in the first segment but not in at least part of the second segment. An insulated gate electrode adjoins the first segment and is configured to provide a first channel region in the first segment, adjoins the second segment and is configured to provide a second channel region in the second segment, and adjoins the source region. During a linear mode of operation, current flows first in the second segment but not in the first segment to reduce the likelihood of thermal runaway.

公开(公告)号：US11687759B2

公开(公告)日：2023-06-27

申请号：US16385192

申请日：2019-04-16

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Ivo Leonardus Coenen ,  Dennis Wayne Mitchler

IPC分类号： G06N3/04 ,  G06N3/08

CPC分类号： G06N3/04 ,  G06N3/08

摘要： A neural network implementation is disclosed. The implementation allows the computations for the neural network to be performed on either an accelerator or a processor. The accelerator and the processor share a memory and communicate over a bus to perform the computations and to share data. The implementation uses weight compression and pruning, as well as parallel processing, to reduce computing, storage, and power requirements.

公开(公告)号：US20230197775A1

公开(公告)日：2023-06-22

申请号：US18169780

申请日：2023-02-15

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Jae-gil LEE ,  Jin-myung KIM ,  Kwang-won LEE ,  Kyoung-deok KIM ,  Ho-cheol JANG

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/08 ,  H01L21/02 ,  H01L29/10 ,  H01L29/66 ,  H01L21/225 ,  H01L21/265 ,  H01L21/324

CPC分类号： H01L29/0634 ,  H01L29/7827 ,  H01L29/0688 ,  H01L29/0886 ,  H01L21/02532 ,  H01L21/02634 ,  H01L21/02381 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/7811 ,  H01L29/0878 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0619

摘要： A semiconductor device having a super junction and a method of manufacturing the semiconductor device capable of obtaining a high breakdown voltage are provided, whereby charge balance of the super junction is further accurately controlled in the semiconductor device that is implemented by an N-type pillar and a P-type pillar. The semiconductor device includes a semiconductor substrate; and a blocking layer including a first conductive type pillar and a second conductive type pillar that extend in a vertical direction on the semiconductor substrate and that are alternately arrayed in a horizontal direction, wherein, in the blocking layer, a density profile of a first conductive type dopant may be uniform in the horizontal direction, and the density profile of the first conductive type dopant may vary in the vertical direction.