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    Reducing stress cracks in substrates
    2.
    发明授权
    Reducing stress cracks in substrates 有权

    公开(公告)号：US11521928B2

    公开(公告)日：2022-12-06

    申请号：US17247094

    申请日：2020-11-30

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Yong Liu ,  Stephen St. Germain

    IPC: H01L23/532 ,  H01L21/768 ,  H01L23/00

    Abstract: Implementations described herein are related to an improved semiconductor device package for providing an electrical connection between one or more semiconductor die and one or more substrates. The one or more substrates includes a dielectric layer having a first side and a second side opposite the first side, and a first metal layer bonded to the first side of the dielectric layer, the first metal layer having a first portion and a second portion. The semiconductor device package can also include a semiconductor die disposed onto the first metal layer within the first portion of the first metal layer. In some implementations, the one or more conducting substrates includes a direct bonded copper (DBC) substrate, i.e., the metal is copper.

    Low stress asymmetric dual side module
    3.
    发明授权
    Low stress asymmetric dual side module 有权

    公开(公告)号：US11469163B2

    公开(公告)日：2022-10-11

    申请号：US16733322

    申请日：2020-01-03

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Chee Hiong Chew ,  Atapol Prajuckamol ,  Stephen St. Germain ,  Yusheng Lin

    IPC: H01L23/367 ,  H01L23/495 ,  H01L23/40 ,  H01L25/065 ,  H01L23/00

    Abstract: Implementations of semiconductor packages may include a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the lead frame.

    Low stress asymmetric dual side module
    4.
    发明授权
    Low stress asymmetric dual side module 有权

    公开(公告)号：US11462515B2

    公开(公告)日：2022-10-04

    申请号：US16678039

    申请日：2019-11-08

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Chee Hiong Chew ,  Atapol Prajuckamol ,  Stephen St. Germain ,  Yusheng Lin

    IPC: H01L23/367 ,  H01L25/07 ,  H01L25/00 ,  H01L23/00

    Abstract: Implementations of semiconductor packages may include: a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include two or more spacers coupled to the first side of the first substrate and a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the two or more spacers.

    Packaging structure for gallium nitride devices
    5.
    发明授权
    Packaging structure for gallium nitride devices 有权

    公开(公告)号：US11107753B2

    公开(公告)日：2021-08-31

    申请号：US16203072

    申请日：2018-11-28

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Stephen St. Germain ,  Roger Arbuthnot ,  David Billings ,  Andrew Celaya

    IPC: H01L23/495 ,  H01L25/065 ,  H01L23/64 ,  H01L21/56 ,  H01L23/31 ,  H01L29/20

    Abstract: Implementations of semiconductor packages may include: a substrate having one or more traces on a first side and one or more traces on a second side of the substrate. The substrate may be rigid. The packages may include at least one die mechanically and electrically coupled to the first side of the substrate. The die may be a high voltage die. The package may include one or more traces along one or more edges of the substrate. The one or more traces along the one or more edges of the substrate provide electrical connectivity between the one or more traces on the first side of the substrate and the one or more traces on the second side of the substrate. The package may also include a molding compound encapsulating at least the first and the one or more edges of the ceramic substrate.

    Semiconductor device and method for supporting ultra-thin semiconductor die
    8.
    发明授权
    Semiconductor device and method for supporting ultra-thin semiconductor die 审中-公开

    公开(公告)号：US10672607B2

    公开(公告)日：2020-06-02

    申请号：US16144750

    申请日：2018-09-27

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Gordon M. Grivna ,  Stephen St. Germain

    IPC: H01L21/02 ,  H01L23/498 ,  H01L23/15 ,  H01L23/14 ,  H01L23/495 ,  H01L21/48 ,  H01L29/20 ,  H01L21/78

    Abstract: A first semiconductor substrate contains a first semiconductor material, such as silicon. A second semiconductor substrate containing a second semiconductor material, such as gallium nitride or aluminum gallium nitride, is formed on the first semiconductor substrate. The first semiconductor substrate and second semiconductor substrate are singulated to provide a semiconductor die including a portion of the second semiconductor material supported by a portion of the first semiconductor material. The semiconductor die is disposed over a die attach area of an interconnect structure. The interconnect structure has a conductive layer and optional active region. An underfill material is deposited between the semiconductor die and die attach area of the interconnect structure. The first semiconductor material is removed from the semiconductor die and the interconnect structure is singulated to separate the semiconductor die. The first semiconductor material can be removed post interconnect structure singulation.

    Single or multi chip module package and related methods
    9.
    发明授权
    Single or multi chip module package and related methods 有权

    公开(公告)号：US10522448B2

    公开(公告)日：2019-12-31

    申请号：US15833533

    申请日：2017-12-06

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Stephen St. Germain ,  Roger M. Arbuthnot ,  Jay A. Yoder ,  Dennis Lee Conner

    IPC: H01L23/498 ,  H01L21/56 ,  H01L23/495 ,  H01L23/31

    Abstract: Implementations of a semiconductor device package may include: a plurality of electrical contacts on a first face of a die, at least one clip electrically and mechanically coupled with at least one electrical contact on a second face of the die where the second face of the die is on an opposing side of the die from the first face of the die. The at least one clip may include at least one lead in electrical communication with the at least one electrical contact on the second face of the die. A mold compound or an encapsulating compound may be included around the die and a majority of the at least one clip where a portion of the at least one lead and a portion of the plurality of electrical contacts on the first face of the die are not overmolded or encapsulated. The semiconductor package includes no lead frame.

    Semiconductor device and method for supporting ultra-thin semiconductor die
    10.
    发明授权
    Semiconductor device and method for supporting ultra-thin semiconductor die 有权

    公开(公告)号：US10090199B2

    公开(公告)日：2018-10-02

    申请号：US15446281

    申请日：2017-03-01

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Gordon M. Grivna ,  Stephen St. Germain

    IPC: H01L21/78 ,  H01L21/02 ,  H01L21/48 ,  H01L29/20 ,  H01L23/495

    Abstract: A first semiconductor substrate contains a first semiconductor material, such as silicon. A second semiconductor substrate containing a second semiconductor material, such as gallium nitride or aluminum gallium nitride, is formed on the first semiconductor substrate. The first semiconductor substrate and second semiconductor substrate are singulated to provide a semiconductor die including a portion of the second semiconductor material supported by a portion of the first semiconductor material. The semiconductor die is disposed over a die attach area of an interconnect structure. The interconnect structure has a conductive layer and optional active region. An underfill material is deposited between the semiconductor die and die attach area of the interconnect structure. The first semiconductor material is removed from the semiconductor die and the interconnect structure is singulated to separate the semiconductor die. The first semiconductor material can be removed post interconnect structure singulation.

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