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公开(公告)号：US20240312495A1
公开(公告)日：2024-09-19
申请号：US18676354
申请日：2024-05-28
Applicant: STMicroelectronics International N.V.
Inventor： Vikas RANA , Arpit VIJAYVERGIA
Abstract: The present disclosure is directed to arranging user data memory cells and test memory cells in a configurable memory array that can perform both differential and single ended read operations during memory start-up and normal memory use, respectively. Different arrangements of the user data memory cells and the test memory cells in the memory array result in increased effectiveness of memory array, in terms of area optimization, memory read accuracy and encryption for data security.
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公开(公告)号：US20240311227A1
公开(公告)日：2024-09-19
申请号：US18122420
申请日：2023-03-16
Applicant: STMicroelectronics International N.V.
Inventor： Avneep Kumar Goyal , Thomas Szurmant
CPC classification number: G06F11/0793 , G06F1/08 , G06F11/0745
Abstract: According to an embodiment, a system is provided that includes a debugging tool and an application board. The debugging tool includes a serial wire debug (SWD) host coupled to a single signal debug port (SSDP) host. The application board includes an SWD target coupled to an SSDP target. The SWD target is configured to communicate SWD signals with the SWD host. The SSDP target is configured to encode the SWD signals to SSDP signals for communication over a Controller Area Network (CAN) Bus between the application board and the debugging tool. The SSDP signals are pulse-width modulation (PWM) encoded signals of the SWD signals. An SWD clock signal generated by the SWD host is the carrier signal for the PWM encoded signals. The SSDP target is configured to decode the SSDP signals received from the SSDP host over the CAN Bus to the SWD signals.
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公开(公告)号：US12095601B2
公开(公告)日：2024-09-17
申请号：US18064593
申请日：2022-12-12
Applicant: STMicroelectronics International N.V.
Inventor： Andrea Mineo , Giovanni Amedeo Cirillo
IPC: H04L27/06
CPC classification number: H04L27/06
Abstract: According to an embodiment, a circuit for decoding a biphase mark coding (BMC) encoded signal is provided. The circuit includes a matched filter, a decoder circuit and a finite state machine (FSM) circuit. The matched filter is configured to generate a first response and a second response to the BMC encoded signal. The first response and second response operate respectively, at a half clock period and a full clock period of the BMC encoded signal. The detector circuit is coupled to an output of the matched filter. The detector circuit is configured to generate an output signal based on detecting a half-bit rise for the first response, a half-bit fall for the first response, a full-bit rise for the second response, or a full-bit fall for the second response. The FSM circuit is configured to decode the BMC encoded signal based on the output signal of the detector circuit.
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公开(公告)号：US20240305197A1
公开(公告)日：2024-09-12
申请号：US18597428
申请日：2024-03-06
Applicant: STMicroelectronics International N.V.
Inventor： David CHESNEAU
IPC: H02M3/158
CPC classification number: H02M3/158
Abstract: A buck switching converter is calibrated using a method which alternates between first and second calibration phases. During each first calibration phase: a time period of low-side switch on state is kept constant and, for each current pulse in an inductor, a sign of a value of the current at the end of the time period of on state of the low-side switch is determined. Modification of a time period of high-side switch on state is made based on the determined sign. During each second calibration phase: a time period of high-side switch on state is kept constant and, for each current pulse in the inductor, a value of the current at the end of the time period of on state of the high-side switch is compared with a target value. Modification of the time period of low-side switch on state is made based on the comparison.
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公开(公告)号：US20240304731A1
公开(公告)日：2024-09-12
申请号：US18594210
申请日：2024-03-04
Applicant: STMicroelectronics International N.V.
Inventor： Francois TAILLIET , Marc BATTISTA
IPC: H01L29/8605 , H01L27/06
CPC classification number: H01L29/8605 , H01L27/0629
Abstract: An electronic device includes first and second diffused resistors in contact with each other to form a PN junction. The device is configured so that a potential difference between the first and second resistors is constant at any point of the PN junction. The PN junction is reverse-biased.
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Patent Agency Ranking
公开(公告)号：US20240304224A1
公开(公告)日：2024-09-12
申请号：US18583568
申请日：2024-02-21
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor： Christophe GONCALVES , Marc BATTISTA , Francois TAILLIET
CPC classification number: G11C7/08 , G11C7/1048 , G11C7/1069
Abstract: The present disclosure relates to a method of reading a word in a memory device, wherein the word is comprised in a first set of words that can be read by the memory device, each word of the first set comprising at least one byte of data, each word being contained in memory cells, the method comprising a pre-charging step during which the first set and at least a second set of words are pre-charged, a first terminal of each cell of the first and second sets being floating during the pre-charging step.
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公开(公告)号：US12088326B2
公开(公告)日：2024-09-10
申请号：US17940236
申请日：2022-09-08
Applicant: STMicroelectronics International N.V.
Inventor： Ankur Bal , Abhishek Jain
CPC classification number: H03M3/464 , H03K3/356 , H03M1/0626 , H03M3/43
Abstract: A continuous time, sigma-delta analog-to-digital converter circuit includes a sigma-delta modulator circuit configured to receive an analog input signal. A single bit quantizer of the modulator generates a digital output signal at a sampling frequency. A data storage circuit stores bits of the digital output signal and digital-to-analog converter (DAC) elements are actuated in response to the stored bits to generate an analog feedback signal for comparison to the analog input signal. A filter circuit includes polyphase signal processing paths and a summation circuit configured to sum outputs from the polyphase signal processing paths to generate a converted output signal. A fan out circuit selectively applies the stored bits from the data storage circuit to inputs of the polyphase signal processing paths of the filter circuit.
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公开(公告)号：US12088085B2
公开(公告)日：2024-09-10
申请号：US18157737
申请日：2023-01-20
Inventor： Manoj Kumar , Ravinder Kumar , Nicolas Demange
CPC classification number: H02H3/20 , H02H1/0007
Abstract: An integrated circuit includes an overvoltage protection circuit. The overvoltage protection circuit detects overvoltage events at a pad of the integrated circuit. The overvoltage protection circuit generates a max voltage signal that is the greater of the voltage at the pad and a supply voltage of the integrated circuit. The overvoltage protection circuit disables a PMOS transistor coupled to the pad by supplying the max voltage signal to the gate of the PMOS transistor when an overvoltage event is present at the pad.
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109.发明公开公开(公告)号：US20240297044A1
公开(公告)日：2024-09-05
申请号：US18583752
申请日：2024-02-21
Applicant: STMicroelectronics International N.V.
Inventor： Cateno Marco CAMALLERI , Mario Giuseppe SAGGIO , Edoardo ZANETTI , Gabriele BELLOCCHI
IPC: H01L21/04
CPC classification number: H01L21/0465
Abstract: A manufacturing process provides for: forming a semiconductor body of silicon carbide, having a front surface; performing a localized ion implantation to form implanted regions in implant portions in the semiconductor body. The step of performing a localized ion implantation provides for: forming damaged regions at the front surface, separated from each other by the implant portions in a direction parallel to the front surface; performing a channeled ion implantation, for implanting doping ions within the semiconductor body and forming the implanted regions at the implant portions of the semiconductor body. The channeled ion implantation is performed in a self-aligned manner with respect to the damaged regions, which represent damaged regions of the silicon-carbide crystallographic lattice such as to block a propagation of the channeled ion implantation along a vertical axis orthogonal to the front surface, in a depth direction of the semiconductor body.
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110.发明公开公开(公告)号：US20240292610A1
公开(公告)日：2024-08-29
申请号：US18586440
申请日：2024-02-24
Applicant: STMicroelectronics International N.V.
Inventor： Pascal FORNARA
Abstract: A memory cell is formed by a PIN diode having three contacts. A breakdown voltage is applied to break down a gate oxide arranged between a region of the PIN diode and a substrate region. The breakdown or non-breakdown state of the gate oxide is determined by applying a read voltage between the anode and the cathode of the diode and determining the value of the corresponding current flowing in the diode.
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