公开(公告)号：US07142070B2

公开(公告)日：2006-11-28

申请号：US10947847

申请日：2004-09-23

Applicant: Stefan Herzinger ,  Günter Märzinger ,  Burkhard Neurauter ,  Robert Weigel

Inventor： Stefan Herzinger ,  Günter Märzinger ,  Burkhard Neurauter ,  Robert Weigel

IPC: H03C3/06

CPC classification number: H03C3/0975 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941

Abstract: A two-point modulator arrangement is specified, said arrangement being developed with respect to conventional two-point modulators to the effect that the high-pass coupling-in point of the modulator that comprises a phase locked loop is formed by an expanded loop filter. In accordance with the present principle, the expanded loop filter comprises a coupling-in element, at which the modulation signal is combined with the output signal of a phase comparator. A voltage-controlled oscillator having only one tuning input can thus advantageously be used.

Abstract translation: 指定了两点调制器布置，所述布置相对于传统的两点调制器被展开，使得包括锁相环的调制器的高通耦合点由扩展环路滤波器形成。 根据本原理，扩展环路滤波器包括耦合入元件，其中调制信号与相位比较器的输出信号组合。 因此，可以有利地使用仅具有一个调谐输入的压控振荡器。

公开(公告)号：US07005925B2

公开(公告)日：2006-02-28

申请号：US10498151

申请日：2002-12-13

Applicant: David Paul Owen ,  Adrian Mark Jones

Inventor： David Paul Owen ,  Adrian Mark Jones

IPC: H03L7/00

CPC classification number: H03C3/095 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03L7/23

Abstract: A low noise sinusoidal signal at a desired output frequency is synchronised using a first variable frequency oscillator (1) and providing a feedback control loop around the first oscillator (1) to generate a feedback control signal in successive frequ comparison steps using second and third frequency reference signals (44, 42). Each of the second and third frequency reference signals are derived from a first frequency reference signal, the second frequency reference signal (44) being compared with the output frequency of the first oscillator (1) to generate a frequency difference signal (43), and said frequency difference signal ( being compared in frequency with the third frequency reference signal (42) to generate said feedback control signal for the first oscillator (1), the frequency of the third frequency reference signal (42) being equal to the difference of the frequency of the se frequency reference signal (44) and the desired output frequency. The second and third frequency reference signals (44, 42) are generated by respective second and third frequency reference sources, the second frequency reference source comprising a second variable frequency oscillator (38) the frequency of which is maintained in a limited range around its optimum natural frequency to give optimum performance in producing a low noise output from the first oscillator (1).

Abstract translation: 使用第一可变频率振荡器（1）使期望输出频率的低噪声正弦信号同步，并且在第一振荡器（1）周围提供反馈控制环路，以在使用第二和第三频率的连续频率比较步骤中产生反馈控制信号 参考信号（44,42）。 第二频率参考信号和第三频率参考信号中的每一个从第一频率参考信号导出，将第二频率参考信号（44）与第一振荡器（1）的输出频率进行比较以产生频率差信号（43），以及 所述频率差信号（频率与第三频率参考信号（42）进行比较）以产生用于第一振荡器（1）的反馈控制信号，第三频率参考信号（42）的频率等于 频率参考信号（44）的频率和期望的输出频率，第二和第三频率参考信号（44,42）由相应的第二和第三频率参考源产生，第二频率参考源包括第二可变频率振荡器 （38），其频率保持在围绕其最佳固有频率的有限范围内，以获得最佳性能 在产生来自第一振荡器（1）的低噪声输出。

公开(公告)号：US06898257B2

公开(公告)日：2005-05-24

申请号：US09788900

申请日：2001-02-20

Applicant: Georg Fischer ,  Volker Riemann

Inventor： Georg Fischer ,  Volker Riemann

IPC: H03C3/08 ,  H03C3/09 ,  H04B1/04 ,  H04L27/20 ,  H03D3/24

CPC classification number: H03C3/0991 ,  H03C3/08 ,  H03C3/0925 ,  H03C3/0941 ,  H03C3/0966 ,  H03C3/0983 ,  H04B2001/0491 ,  H04L27/2017

Abstract: The invention relates, inter alia, to a transmitter device, in particular for a base transceiver station in a mobile radio system, which has a digital modulator for making available a signal containing a phase information, and a modulation closed loop having a digital phase comparator operating at baseband whose first input is connected to the output of the digital modulator. In addition, a controllable oscillator is provided for generating an RF transmission signal at a controllable transmission frequency, a device which is assigned to the controllable oscillator and has the purpose of converting the RF transmission signal into a baseband signal containing a phase information. The output of the converter device is connected to a second input of the digital phase comparator.A GSM transmitter which has such a modulation closed loop exhibits, in terms of its out-band noise and interference characteristics, significantly improved properties in comparison with a GSM transmitter which does not include a modulation loop.

Abstract translation: 本发明尤其涉及一种发射机设备，特别是涉及一种移动无线电系统中的基站收发信机，其具有用于提供包含相位信息的信号的数字调制器和具有数字相位比较器的调制闭环 在基带处工作，其第一输入连接到数字调制器的输出端。 此外，提供可控制的振荡器，用于以可控的传输频率产生RF传输信号，分配给可控振荡器的装置，并且其目的是将RF传输信号转换成包含相位信息的基带信号。 转换器装置的输出连接到数字相位比较器的第二输入端。 与不包括调制环路的GSM发射机相比，具有这种调制闭环的GSM发射机在其带外噪声和干扰特性方面表现出显着改善的特性。

公开(公告)号：US20050084034A1

公开(公告)日：2005-04-21

申请号：US10923351

申请日：2004-08-20

Applicant: Markus Hammes ,  Giuseppe Puma ,  Stefan Waasen

Inventor： Markus Hammes ,  Giuseppe Puma ,  Stefan Waasen

IPC: H03C3/09 ,  H04L27/04

CPC classification number: H03C3/095 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941

Abstract: A PLL circuit (1) is regulated by means of a digital modulation signal (28) at a first frequency, and is then regulated at a second frequency, by deactivation of the digital modulation signal (28). A difference signal (32), which is characteristic of the voltage change in a control signal (22) for the VCO (7) which is produced by deactivation of the digital modulation signal (28) is compared with an analog modulation signal (34). The analog modulation signal (34) is changed so as to correct any discrepancy determined during the comparison.

Abstract translation: PLL电路（1）借助于第一频率的数字调制信号（28）进行调节，然后通过停止数字调制信号（28）以第二频率调节。 将通过停止数字调制信号（28）产生的用于VCO（7）的控制信号（22）中的电压变化的特征的差分信号（32）与模拟调制信号（34）进行比较， 。 改变模拟调制信号（34）以便校正在比较期间确定的任何差异。

公开(公告)号：US20050073368A1

公开(公告)日：2005-04-07

申请号：US10498151

申请日：2002-12-13

Applicant: David Owen ,  Adrian Jones

Inventor： David Owen ,  Adrian Jones

IPC: H03L7/183 ,  H03C3/09 ,  H03L7/197 ,  H03L7/23 ,  H03L7/00

CPC classification number: H03C3/095 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03L7/23

Abstract: A low noise sinusoidal signal at a desired output frequency is synchronised using a first variable frequency oscillator (1) and providing a feedback control loop around the first oscillator (1) to generate a feedback control signal in successive frequency comparison steps using second and third frequency reference signals (44, 42). Each of the second and third frequency reference signals are derived from a first frequency reference signal, the second frequency reference signal (44) being compared with the output frequency of the first oscillator (1) to generate a frequency difference signal (43), and said frequency difference signal (43) being compared in frequency with the third frequency reference signal (42) to generate said feedback control signal for the first oscillator (1), the frequency of the third frequency reference signal (42) being equal to the difference of the frequency of the second frequency reference signal (44) and the desired output frequency. The second and third frequency reference signals (44, 42) are generated by respective second and third frequency reference sources, the second frequency reference source comprising a second variable frequency oscillator (38) the frequency of which is maintained in a limited range around its optimum natural frequency to give optimum performance in producing a low noise output from the first oscillator (1).

Abstract translation: 使用第一可变频率振荡器（1）同步所需输出频率的低噪声正弦信号，并在第一振荡器（1）周围提供反馈控制环路，以在连续频率比较步骤中使用第二和第三频率产生反馈控制信号 参考信号（44,42）。 第二频率参考信号和第三频率参考信号中的每一个从第一频率参考信号导出，将第二频率参考信号（44）与第一振荡器（1）的输出频率进行比较以产生频率差信号（43），以及 所述频率差信号（43）在频率上与第三频率参考信号（42）进行比较，以产生第一振荡器（1）的反馈控制信号，第三频率参考信号（42）的频率等于差分 的第二频率参考信号（44）的频率和期望的输出频率。 第二和第三频率参考信号（44,42）由相应的第二和第三频率参考源产生，第二频率参考源包括第二可变频率振荡器（38），其频率被保持在围绕其最佳值的有限范围内 以产生来自第一振荡器（1）的低噪声输出的最佳性能。

公开(公告)号：US20040146098A1

公开(公告)日：2004-07-29

申请号：US10758913

申请日：2004-01-16

Applicant: Texas Instruments Incorporated

Inventor： Oren Eliezer ,  Bogdan Staszewski ,  Ofer Friedman

IPC: H03C003/06

CPC classification number: H03C3/0991 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0966 ,  H03L2207/50

Abstract: An on-chip reduced complexity modulation noise estimation mechanism for performing nonlinear signal processing to analyze modulation noise to determine whether a semiconductor device under test complies with the performance criteria set by specifications or a standard corresponding thereto. When used in a two-point transmitter modulation architecture, the mechanism relies on the fact that the noise statistics at the output of the transmitter can be determined by observing the phase error output of the phase detector within the phase locked loop. In the digital embodiment of the mechanism, the phase error signal is compared to a configurable threshold value to generate an exception event. If the number of exception events exceeds a configurable max_fail value after comparisons of a configurable number of phase error samples, the test fails. A pass/fail signal is output reflecting the result of the test. The test comprises a configurable number of test samples to permit flexibility in the tradeoff between the time required to complete the test versus the statistical reliability of the test result, i.e. the probability of it correctly determining whether the tested device complies with target specifications.

Abstract translation: 一种用于执行非线性信号处理以分析调制噪声以确定被测半导体器件是否符合由规范或相应的标准设置的性能标准的片上缩减复杂度调制噪声估计机制。 当用于两点发射机调制架构时，该机制依赖于以下事实：可以通过观察锁相环内的相位检测器的相位误差输出来确定发射机输出端的噪声统计。 在该机构的数字实施例中，将相位误差信号与可配置的阈值进行比较以产生异常事件。 如果在比较可配置数量的相位误差样本之后异常事件的数量超过可配置的max_fail值，则测试失败。 输出反映测试结果的通过/失败信号。 该测试包括可配置数量的测试样本，以允许在完成测试所需的时间与测试结果的统计可靠性之间进行权衡的灵活性，即，其正确确定被测试设备是否符合目标规范的概率。

公开(公告)号：US06734749B2

公开(公告)日：2004-05-11

申请号：US09867921

申请日：2001-05-29

Applicant: Sven Mattisson ,  Håkan Eriksson

Inventor： Sven Mattisson ,  Håkan Eriksson

IPC: H03C300

CPC classification number: H03C3/0975 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095

Abstract: Direct frequency modulation of a phase-locked loop (PLL) output signal is achieved by means of a modulation signal comprising a digital sequence. The digital modulation signal is coupled to the input of the VCO of the PLL, and is also coupled to drive an up-down counter. The output of the counter is coupled to a D/A converter to provide a compensation signal for the PLL. When the counter output reaches values representing modulation-induced phase errors of +360 degrees and −360 degrees, the counter generates signals respectively corresponding thereto to adjust the PLL frequency divider.

Abstract translation: 通过包括数字序列的调制信号来实现锁相环（PLL）输出信号的直接频率调制。 数字调制信号耦合到PLL的VCO的输入，并且还耦合以驱动上下计数器。 计数器的输出耦合到D / A转换器，为PLL提供补偿信号。 当计数器输出达到表示+ 360度和-360度的调制诱发相位误差的值时，计数器产生分别对应的信号以调整PLL分频器。

公开(公告)号：US06734741B2

公开(公告)日：2004-05-11

申请号：US10006607

申请日：2001-11-30

Applicant: Robert B. Staszewski ,  Dirk Leipold ,  Khurram Muhammad ,  Chih-Ming Hung

Inventor： Robert B. Staszewski ,  Dirk Leipold ,  Khurram Muhammad ,  Chih-Ming Hung

IPC: H03L700

CPC classification number: H03C3/0975 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0958 ,  H03C3/0966 ,  H03K19/0016 ,  H03L7/085 ,  H03L7/087 ,  H03L7/091 ,  H03L7/093 ,  H03L7/099 ,  H03L7/16 ,  H03L2207/50 ,  H04L7/0029

Abstract: A transmitter (10) based on a frequency synthesizer includes an LC tank (12) of a digitally controlled oscillator (DCO) with various arrays of capacitors. The LC tank 12 is divided into two major groups that reflect two general operational modes: acquisition and tracking. The first group (process/voltage/temperature and acquisition) approximately sets the desired center frequency of oscillation initially, while the second group (integer and fractional tracking) precisely controls the oscillating frequency during the actual operation. For highly accurate outputs, dynamic element matching (DEM) is used in the integer tracking controller to reduce non-linearities caused by non-uniform capacitor values. Also, a preferred range of the integer tracking capacitor array may be used for modulation after the selected channel has been acquired. A digital sigma-delta modulator circuit (50) drives a capacitor array (14d) in response to the fractional bits of the error word. On mode switches, the accumulated error is recalculated to a phase restart value to prevent perturbations.

公开(公告)号：US20040066240A1

公开(公告)日：2004-04-08

申请号：US10679792

申请日：2003-10-06

Inventor： Robert B. Staszewski ,  Dirk Leipold ,  Khurram Muhammad ,  Chih-Ming Hung

IPC: H03L007/00

CPC classification number: H03C3/0975 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0958 ,  H03C3/0966 ,  H03K19/0016 ,  H03L7/085 ,  H03L7/087 ,  H03L7/091 ,  H03L7/093 ,  H03L7/099 ,  H03L7/16 ,  H03L2207/50 ,  H04L7/0029

Abstract: A transmitter (10) based on a frequency synthesizer includes an LC tank (12) of a digitally controlled oscillator (DCO) with various arrays of capacitors. The LC tank 12 is divided into two major groups that reflect two general operational modes: acquisition and tracking. The first group (process/voltage/temperature and acquisition) approximately sets the desired center frequency of oscillation initially, while the second group (integer and fractional tracking) precisely controls the oscillating frequency during the actual operation. For highly accurate outputs, dynamic element matching (DEM) is used in the integer tracking controller to reduce non-linearities caused by non-uniform capacitor values. Also, a preferred range of the integer tracking capacitor array may be used for modulation after the selected channel has been acquired. A digital sigma-delta modulator circuit (50) drives a capacitor array (14d) in response to the fractional bits of the error word. On mode switches, the accumulated error is recalculated to a phase restart value to prevent perturbations.

公开(公告)号：US06268780B1

公开(公告)日：2001-07-31

申请号：US09558927

申请日：2000-04-26

Applicant: Christian Olgaard ,  Benny Madsen

Inventor： Christian Olgaard ,  Benny Madsen

IPC: H03L708

CPC classification number: H03C3/0975 ,  H03C3/0941 ,  H03C3/0958 ,  H03L7/14 ,  H03L7/181 ,  H03L2207/10

Abstract: A frequency synthesizer with a digital frequency lock loop (FLL) having a fast frequency lock time uses a frequency counter circuit in the feedback loop to count the output signal frequency and produce frequency count data. A modulation control circuit provides modulation data and a corresponding modulation control signal for modulating the FLL signal source. A microprocessor processes the frequency count data along with the modulation data to provide a frequency control signal for controlling the nominal, or center, frequency of the FLL signal source. By processing these data together, thereby accounting for the amount of modulation applied to the FLL signal source, the center frequency can be maintained more consistently notwithstanding the presence of modulation within the feedback loop signal.

Abstract translation: 具有快速锁定时间的数字频率锁定环（FLL）的频率合成器使用反馈回路中的频率计数器电路对输出信号频率进行计数并产生频率计数数据。 调制控制电路提供用于调制FLL信号源的调制数据和相应的调制控制信号。 微处理器与调制数据一起处理频率计数数据，以提供用于控制FLL信号源的标称或中心频率的频率控制信号。 通过将这些数据一起处理，从而考虑了施加到FLL信号源的调制量，即使反馈环路信号中存在调制，中心频率也可以保持一致。