公开(公告)号：US20020122340A1

公开(公告)日：2002-09-05

申请号：US10002599

申请日：2001-10-31

Applicant: STMicroelectronics S.r.I

Inventor： Rino Micheloni ,  Andrea Sacco

IPC: G11C016/04

CPC classification number: G11C16/24 ,  G11C16/10

Abstract: A pulse programming method for a non-volatile memory device includes: addressing memory cells to be programmed within the device by selecting corresponding hierarchic decoder transistors; biasing the gate terminals of the memory cells; and programming the memory cells by applying a voltage pulse, regulated by a bias circuit, to the drain terminals of the memory cells. Advantageously, the programming method further comprises a step of precharging an internal node of the bias circuit before starting the programming step, the internal node being connected to a parasitic capacitance of the memory device.

Abstract translation: 一种用于非易失性存储器件的脉冲编程方法包括：通过选择相应的层级解码器晶体管寻址要在器件内编程的存储器单元; 偏置存储单元的栅极端子; 以及通过将由偏置电路调节的电压脉冲施加到存储器单元的漏极端子来对存储器单元进行编程。 有利地，编程方法还包括在开始编程步骤之前对偏置电路的内部节点进行预充电的步骤，内部节点连接到存储器件的寄生电容。

公开(公告)号：US20020120908A1

公开(公告)日：2002-08-29

申请号：US10061949

申请日：2002-01-31

Applicant: STMicroelectronics S.r.I.

Inventor： Amedeo La Scala

IPC: G06F017/50

CPC classification number: G01R31/318505 ,  G01R31/318558

Abstract: Management of Test Access Port functions of a plurality of components arranged on a single chip by selectively driving the TAP function of each of the components with respective clocks, whilst the further signals for driving the TAP function are used in a shared mode among the various components. Preferably, associated with the aforesaid clocks is a pull-down function for selectively blanking the respective clocks in conditions of non-use. In a preferred way, the aforesaid dedicated clocks are generated on board the chip.

Abstract translation: 管理测试访问通过选择性地以相应的时钟驱动每个组件的TAP功能，同时在各种组件中以共享模式使用用于驱动TAP功能的另外的信号，在单个芯片上布置的多个组件的端口功能 。 优选地，与上述时钟相关联的是用于在不使用的条件下选择性地消隐各个时钟的下拉功能。 在优选的方式中，上述专用时钟在芯片上产生。

公开(公告)号：US20020079948A1

公开(公告)日：2002-06-27

申请号：US09912073

申请日：2001-07-24

Applicant: STMicroelectronics S.r.I.

Inventor： Ugo Moriconi ,  Claudio Adragna

IPC: H03K017/16

CPC classification number: H03K17/063 ,  H02M3/155 ,  H02M3/1588 ,  Y02B70/1466

Abstract: The present invention concerns a bootstrap circuit in DC/DC static converters comprising first current generator means controlled to close in function of a first signal and a recharge circuit of a capacitor. The bootstrap circuit has the characteristic of comprising second current generator means controlled to close with a second signal synchronous with the first signal, the second signal has times and modalities such to send to the capacitor recharge currents such to compensate the discharge of the capacitor itself.

Abstract translation: 本发明涉及DC / DC静态转换器中的自举电路，其包括被控制为关闭第一信号和电容器的再充电电路的第一电流发生器装置。 自举电路具有包括被控制为与第一信号同步的第二信号闭合的第二电流发生器装置的特性，第二信号具有发送到电容器再充电电流以补偿电容器本身的放电的次数和模态。

公开(公告)号：US20020074607A1

公开(公告)日：2002-06-20

申请号：US10077288

申请日：2002-02-15

Applicant: STMicroelectronics, S.r.I.

Inventor： Loris Vendrame ,  Paolo Ghezzi

IPC: H01L029/94

CPC classification number: H01L29/0692 ,  H01L21/8249 ,  H01L29/7322

Abstract: A bipolar transistor is produced by processes employed in the manufacture of CMOS nonvolatile memory devices, and is part of an integrated circuit. The integrated circuit includes a semiconductor substrate having a first type of conductivity, a PMOS transistor formed in said substrate, an NMOS transistor formed in said substrate, and the bipolar transistor. The bipolar transistor includes: a buried semiconductor layer having a second type of conductivity placed at a prescribed depth from the surface of said bipolar transistor, an isolation semiconductor region having the second type of conductivity, in direct contact with said buried semiconductor layer, and suitable for delimiting a portion of said substrate, forming a base region; an emitter region formed within said base region having the second type of conductivity, a base contact region of said transistor formed within said base region having the first type of conductivity, a collector contact region formed within said isolation semiconductor region having the second type of conductivity, wherein said base region has a doping concentration between 1016 and 1017 atoms/cm3.

Abstract translation: 双极晶体管是通过制造CMOS非易失性存储器件的工艺生产的，并且是集成电路的一部分。 集成电路包括具有第一导电类型的半导体衬底，形成在所述衬底中的PMOS晶体管，形成在所述衬底中的NMOS晶体管和双极晶体管。 所述双极晶体管包括：具有从所述双极晶体管的表面设置在规定深度的第二导电类型的掩埋半导体层，具有与所述掩埋半导体层直接接触的第二导电类型的隔离半导体区域， 用于限定所述衬底的一部分，形成基部区域; 形成在具有第二导电类型的所述基极区内的发射极区域，形成在具有第一导电类型的所述基极区域内的所述晶体管的基极接触区域，形成在具有第二导电类型的所述隔离半导体区域内的集电极接触区域 ，其中所述碱性区域的掺杂浓度为1016至1017原子/ cm3。

公开(公告)号：US20020020872A1

公开(公告)日：2002-02-21

申请号：US09976484

申请日：2001-10-12

Applicant: STMicroelectronics S.r.I.

Inventor： Carlo Cremonesi ,  Bruno Vajana ,  Roberta Bottini ,  Giovanna Dalla Libera

IPC: H01L029/788 ,  H01L029/76 ,  H01L029/792

CPC classification number: H01L27/11521 ,  H01L21/2652 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/66825

Abstract: A process formes a structure incorporating at least one circuitry transistor and at least one non-volatile memory cell of the EEPROM type with two self-aligned polysilicon levels having a storage transistor and an associated selection transistor in a substrate of semiconductor material including field oxide regions bounding active area regions. The process comprises the steps of in the active area regions, forming a gate oxide layer and defining a tunnel oxide region included in the gate oxide layer depositing and partly defining a first polysilicon layer forming an interpoly dielectric layer and removing the interpoly dielectric layer at least at the circuitry transistor depositing a second polysilicon layer selectively etching away the second polysilicon layer at the cell, and the first and second polysilicon layers at the circuitry transistor and selectively etching away the interpoly dielectric layer and the first polysilicon layer at the cell. After forming and before partially defining the first polysilicon layer, the process implants at least at the channel region of the floating-gate storage transistor for adjusting the transistor threshold.

Abstract translation: 一种工艺形成了结合有至少一个电路晶体管和EEPROM型的至少一个非易失性存储单元的结构，其中两个自对准多晶硅层具有存储晶体管和相关选择晶体管，该半导体材料包括场氧化物区域 边界活跃区域。 该方法包括以下步骤：在有源区域中，形成栅极氧化物层并限定栅极氧化物层中包括的隧道氧化物区域，沉积并部分地限定形成多晶硅互连层的第一多晶硅层，并至少除去多晶硅绝缘层 在电路晶体管处沉积第二多晶硅层选择性地蚀刻掉电池处的第二多晶硅层，以及在电路晶体管处的第一和第二多晶硅层，并且选择性地蚀刻离开电池的多晶硅间介电层和第一多晶硅层。 在形成之后并且在部分地限定第一多晶硅层之前，该工艺至少在浮栅存储晶体管的沟道区域处注入以调整晶体管阈值。

公开(公告)号：US20020018390A1

公开(公告)日：2002-02-14

申请号：US09909467

申请日：2001-07-19

Applicant: STMicroelectronics S.r.I.

Inventor： Emanuele Confalonieri ,  Lorenzo Bedarida ,  Mauro Sali ,  Simone Bartoli

IPC: G11C005/14

CPC classification number: G11C16/30

Abstract: A semiconductor memory includes a plurality of memory cells connected to one another to form a matrix of memory cells. A charge pump is connected to the matrix of memory cells. A plurality of controllable connection elements are provided, with each controllable connection element connected between an output terminal of the charge pump and a respective column line. Connected to the output of the charge pump is the series connection of a first element equivalent to a controllable connection element, and a second element equivalent to a memory cell in a predetermined biasing condition. A voltage regulator is connected between the second equivalent element and the input terminal of the charge pump for regulating the output voltage therefrom based upon a voltage present between terminals of the second equivalent element.

公开(公告)号：US20010036115A1

公开(公告)日：2001-11-01

申请号：US09817804

申请日：2001-03-26

Applicant: STMicroelectronics S.r.I.

Inventor： Alessandro Rocchi ,  Marco Bisio ,  Marco Pasotti ,  Pier Luigi Rolandi

IPC: G11C007/00

CPC classification number: G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7211

Abstract: A FLASH memory is organized in a plurality of physical sectors which may be split into a plurality of singularly addressable logic sectors. Each logic sector may include a memory space of a predetermined size and a chain pointer assuming a neutral value or a value pointing to a second logic sector associated with a respective chain pointer at the neutral value. Each logic sector may also include a status indicator assuming at least one of a first value if the logic sector is empty, a second value if the data therein belongs to the logic sector, a third value if the data does not belong to the logic sector, and a fourth value if the data has been erased. Further, each logic sector may include a remap pointer assuming the neutral value or a value pointing directly or indirectly to the chain pointer of a third logic sector.

Abstract translation: 闪存存储器被组织在多个物理扇区中，这些物理扇区可被分成多个可单独寻址的逻辑扇区。 每个逻辑扇区可以包括预定大小的存储器空间和假定中性值的链指针或指向与中性值处的相应链指针相关联的第二逻辑扇区的值。 如果逻辑扇区为空，则每个逻辑扇区还可以包括状态指示符，如果其中的数据属于逻辑扇区，则假设第二值为第一值;如果数据不属于逻辑扇区，则第三值 ，如果数据已被擦除，则为第四个值。 此外，每个逻辑扇区可以包括假定中性值的重映射指针或直接或间接指向第三逻辑扇区的链指针的值。

公开(公告)号：US20240095057A1

公开(公告)日：2024-03-21

申请号：US18457229

申请日：2023-08-28

Applicant: STMicroelectronics S.r.I.

Inventor： Giampiero Borgonovo ,  Lorenzo Re Fiorentin

IPC: G06F9/455

CPC classification number: G06F9/45558 ,  G06F2009/45583 ,  G06F2009/45595

Abstract: A system, for use in providing media access control (MAC)/router/switch/gateway features in an on-board communication network in a vehicle, includes MAC controllers configured to provide a MAC port layer controlling exchange of information over a data link, virtual machine (VM) bridge blocks configured to provide a MAC frame layer interfacing with System-on-Chip VMs, a software (SW) Ethernet port configured to receive from a host programming/configuration information for the system, a local memory controller configured to facilitate the MAC controllers, the VM bridge blocks and the SW Ethernet port in cooperating with a local memory (LMEM), and queue handlers configured to provide queue management for the MAC controllers, the VM bridge blocks and the SW Ethernet port, during cooperation with the LMEM via the local memory controller.

公开(公告)号：US20230376229A1

公开(公告)日：2023-11-23

申请号：US17663847

申请日：2022-05-18

Applicant: STMicroelectronics S.r.I.

Inventor： Walter Girardi

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0602 ,  G06F3/0671

Abstract: A circuit for reading or writing a RAM includes a shift register coupled to the RAM, a test data input, and a test data output. The circuit further includes a control circuit configured to generate a pulse every N clock cycles, each pulse triggering a RAM access operation transferring data between the shift register and the RAM, N being equal to a data width of the RAM divided by a parallel factor, the parallel factor being a number of pins in either the test data input or the test data output configured for parallel data loading.

公开(公告)号：US20230360716A1

公开(公告)日：2023-11-09

申请号：US18349565

申请日：2023-07-10

Applicant: STMicroelectronics S.r.I.

Inventor： Giampiero Borgonovo ,  Lorenzo Re Fiorentin

IPC: G11C29/42 ,  G11C29/12 ,  G11C29/18 ,  G11C29/44

CPC classification number: G11C29/42 ,  G11C29/12015 ,  G11C29/18 ,  G11C29/4401

Abstract: A device includes a set of processing circuits arranged in subsets, a set of data memory banks coupled to a memory controller, a control unit, and an interconnect network. The processing circuits are configurable to read first input data from the data memory banks via the interconnect network and the memory controller, process the first input data to produce output data, and write the output data into the data memory banks via the interconnect network and the memory controller. The hardware accelerator device includes a set of configurable lock-step control units which interface the processing circuits to the interconnect network. Each configurable lock-step control unit is coupled to a subset of processing circuits and is selectively activatable to operate in a first operation mode, or in a second operation mode.