公开(公告)号：US08501523B2

公开(公告)日：2013-08-06

申请号：US10977186

申请日：2004-10-28

Applicant: Jong-Won Lee ,  Kuo-Wei Chang ,  Michael L. McSwiney

Inventor： Jong-Won Lee ,  Kuo-Wei Chang ,  Michael L. McSwiney

IPC: H01L21/00 ,  H01L21/31

CPC classification number: H01L45/06 ,  C23C16/34 ,  H01L27/2427 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/141 ,  H01L45/16 ,  H01L45/1683

Abstract: Organometallic precursors may be utilized to form titanium silicon nitride films that act as heaters for phase change memories. By using a combination of TDMAT and TrDMASi, for example in a metal organic chemical vapor deposition chamber, a relatively high percentage of silicon may be achieved in reasonable deposition times, in some embodiments. In one embodiment, two separate bubblers may be utilized to feed the two organometallic compounds in gaseous form to the deposition chamber so that the relative proportions of the precursors can be readily controlled.

Abstract translation: 有机金属前体可用于形成用作相变存储器的加热器的氮化钛膜。 通过使用TDMAT和TrDMASi的组合，例如在金属有机化学气相沉积室中，在一些实施方案中，可以在合理的沉积时间内实现相对高百分比的硅。 在一个实施方案中，可以使用两个分开的起泡器将气态形式的两种有机金属化合物进料到沉积室，以便容易地控制前体的相对比例。

公开(公告)号：US08400846B2

公开(公告)日：2013-03-19

申请号：US13280199

申请日：2011-10-24

Applicant: Shin Ho Chu ,  Jong Won Lee

Inventor： Shin Ho Chu ,  Jong Won Lee

IPC: G11C7/10 ,  G11C7/00 ,  G11C8/00

CPC classification number: G11C29/18 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/2602

Abstract: A semiconductor integrated circuit includes a multi-mode control signal generating unit configured to control an activation of a up/down mat I/O switch control signal, which controls I/O switches in a up/down mat, according to a multi-test mode signal and a read/write discriminating signal, a multi-mode decoder configured to output multi-mat select signals to simultaneously activate a plurality of mats according to a multi-test mode active write signal, and a mat controller configured to enable word lines and the I/O switches according to the up/down mat I/O switch control signal and the multi-mat select signals.

Abstract translation: 半导体集成电路包括：多模控制信号生成单元，被配置为根据多重测试来控制上/下按钮I / O开关控制信号的激活，其控制上/下垫中的I / O开关 模式信号和读/写鉴别信号;多模式解码器，被配置为输出多个席选择信号，以根据多测试模式有效写入信号同时激活多个地址;以及矩阵控制器，被配置为使得字线 和I / O开关根据上/下垫I / O开关控制信号和多功能选择信号。

公开(公告)号：US08399327B2

公开(公告)日：2013-03-19

申请号：US13240560

申请日：2011-09-22

Applicant: Jong-Won Lee ,  Jae-Seok Kim ,  Bo-Un Yoon

Inventor： Jong-Won Lee ,  Jae-Seok Kim ,  Bo-Un Yoon

IPC: H01L21/336

CPC classification number: H01L21/823842 ,  H01L21/823437 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7835

Abstract: A method includes forming a plurality of dummy gate structures on a substrate, each dummy gate structure including a dummy gate electrode and a dummy gate mask, forming a first insulation layer on the substrate and the dummy gate structures to fill a first space between the dummy gate structures, planarizing upper portions of the first insulation layer and the dummy gate structures, removing the remaining first insulation layer to expose a portion of the substrate, forming an etch stop layer on the remaining dummy gate structures and the exposed portion of the substrate, forming a second insulation layer on the etch stop layer to fill a second space between the dummy gate structures, planarizing upper portions of the second insulation layer and the etch stop layer to expose the dummy gate electrodes, removing the exposed dummy gate electrodes to form trenches, and forming metal gate electrodes in the trenches.

Abstract translation: 一种方法包括在衬底上形成多个虚拟栅极结构，每个虚拟栅极结构包括伪栅极电极和伪栅极掩模，在衬底上形成第一绝缘层和虚拟栅极结构以填充虚拟栅极结构之间的第一空间 栅极结构，平坦化第一绝缘层和伪栅极结构的上部，去除剩余的第一绝缘层以暴露衬底的一部分，在剩余的虚设栅极结构和衬底的暴露部分上形成蚀刻停止层， 在所述蚀刻停止层上形成第二绝缘层以填充所述虚拟栅极结构之间的第二空间，平坦化所述第二绝缘层的上部和所述蚀刻停止层以暴露所述伪栅电极，去除所述暴露的伪栅电极以形成沟槽 并且在沟槽中形成金属栅电极。

公开(公告)号：US20120282752A1

公开(公告)日：2012-11-08

申请号：US13553948

申请日：2012-07-20

Applicant: Jong Won Lee ,  DerChang Kau ,  Gianpaolo Spadini

Inventor： Jong Won Lee ,  DerChang Kau ,  Gianpaolo Spadini

IPC: H01L21/8239

CPC classification number: H01L45/1675 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

Abstract: In one or more embodiments, methods of fabricating current-confining stack structures in a phase change memory switch (PCMS) cell are provided. One embodiment shows a method of fabricating a PCMS cell with current in an upper chalcogenide confined in the row and column directions. In one embodiment, methods of fabricating a PCMS cell with sub-lithographic critical dimension memory chalcogenide are shown. In another embodiment, methods of fabricating a PCMS cell with sub-lithographic critical dimension middle electrode heaters are disclosed.

Abstract translation: 在一个或多个实施例中，提供了在相变存储器开关（PCMS）单元中制造电流限制堆叠结构的方法。 一个实施例示出了制造具有限制在行和列方向上的上硫属化物中的电流的PCMS电池的方法。 在一个实施例中，示出了制造具有亚光刻临界尺度存储硫族化物的PCMS单元的方法。 在另一个实施例中，公开了制造具有亚光刻临界尺寸中间电极加热器的PCMS单元的方法。

公开(公告)号：US08272229B2

公开(公告)日：2012-09-25

申请号：US12320364

申请日：2009-01-23

Applicant: Jei Min Choi ,  Jai Kwon Lee ,  Do Yeon Kim ,  Dae Sung Lee ,  Jong Ki Jeon ,  Jong Won Lee ,  Kang Min Lee

Inventor： Jei Min Choi ,  Jai Kwon Lee ,  Do Yeon Kim ,  Dae Sung Lee ,  Jong Ki Jeon ,  Jong Won Lee ,  Kang Min Lee

IPC: F25D23/12

CPC classification number: F24F1/0007 ,  F24F1/0022 ,  F24F11/33 ,  F24F13/20 ,  F24F2001/004 ,  F24F2013/207

Abstract: Disclosed is an air conditioner having a control box assembly, which enhances the serviceability of a circuit board and reduces production costs. In the air conditioner, which has a casing unit forming an external appearance of the air conditioner, a heat exchanger, a blowing device, and a control box assembly provided in the casing, the control box assembly includes a mounting unit mounting a circuit board; a control box housing the circuit board and the mounting unit; and guide units provided in the control box to guide a rectilinear reciprocating motion of the mounting unit to allow the mounting unit to come into and out of the control box and guide a rotating motion of the mounting unit in the case that the mounting unit is located at a designated position.

Abstract translation: 公开了一种具有控制箱组件的空调器，其提高了电路板的可用性并降低了生产成本。 在具有形成空调的外观的壳体单元的空调机中，设置在壳体中的热交换器，吹风装置和控制箱组件，控制箱组件包括安装电路板的安装单元; 容纳电路板和安装单元的控制箱; 以及设置在所述控制箱中的导向单元以引导所述安装单元的直线往复运动，以允许所述安装单元进出所述控制箱并且引导所述安装单元在所述安装单元所在的情况下的旋转运动 在指定的位置。

公开(公告)号：US20120168687A1

公开(公告)日：2012-07-05

申请号：US13411976

申请日：2012-03-05

Applicant: Branko N. Popov ,  Jong-Won Lee

Inventor： Branko N. Popov ,  Jong-Won Lee

IPC: H01B1/08 ,  H01B1/04

CPC classification number: H01M4/54 ,  H01M4/06 ,  H01M4/364 ,  H01M4/382 ,  H01M4/60 ,  H01M4/606 ,  H01M6/16

Abstract: In one embodiment of the present disclosure, a composite electrode for a battery is provided. The composite electrode includes silver vanadium oxide present in an amount from about 75 weight percent to about 99 weight percent and polypyrrole present in an amount from about 1 weight percent to about 25 weight percent.

Abstract translation: 在本公开的一个实施例中，提供了一种用于电池的复合电极。 复合电极包括以约75重量％至约99重量％的量存在的银钒氧化物，并且存在量为约1重量％至约25重量％的聚吡咯。

公开(公告)号：US20120122283A1

公开(公告)日：2012-05-17

申请号：US13240560

申请日：2011-09-22

Applicant: Jong-Won LEE ,  Jae-Seok Kim ,  Bo-Un Yoon

Inventor： Jong-Won LEE ,  Jae-Seok Kim ,  Bo-Un Yoon

IPC: H01L21/336 ,  H01L21/28

CPC classification number: H01L21/823842 ,  H01L21/823437 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7835

Abstract: A method includes forming a plurality of dummy gate structures on a substrate, each dummy gate structure including a dummy gate electrode and a dummy gate mask, forming a first insulation layer on the substrate and the dummy gate structures to fill a first space between the dummy gate structures, planarizing upper portions of the first insulation layer and the dummy gate structures, removing the remaining first insulation layer to expose a portion of the substrate, forming an etch stop layer on the remaining dummy gate structures and the exposed portion of the substrate, forming a second insulation layer on the etch stop layer to fill a second space between the dummy gate structures, planarizing upper portions of the second insulation layer and the etch stop layer to expose the dummy gate electrodes, removing the exposed dummy gate electrodes to form trenches, and forming metal gate electrodes in the trenches.

Abstract translation: 一种方法包括在衬底上形成多个虚拟栅极结构，每个虚拟栅极结构包括伪栅极电极和伪栅极掩模，在衬底上形成第一绝缘层和虚拟栅极结构以填充虚拟栅极结构之间的第一空间 栅极结构，平坦化第一绝缘层和伪栅极结构的上部，去除剩余的第一绝缘层以暴露衬底的一部分，在剩余的虚设栅极结构和衬底的暴露部分上形成蚀刻停止层， 在所述蚀刻停止层上形成第二绝缘层以填充所述虚拟栅极结构之间的第二空间，平坦化所述第二绝缘层的上部和所述蚀刻停止层以暴露所述伪栅电极，去除所述暴露的伪栅电极以形成沟槽 并且在沟槽中形成金属栅电极。

公开(公告)号：US20120074595A1

公开(公告)日：2012-03-29

申请号：US13191843

申请日：2011-07-27

Applicant: JeongOh Ha ,  Heungkyu Kwon ,  YunSeok Choi ,  Jong-Won Lee

Inventor： JeongOh Ha ,  Heungkyu Kwon ,  YunSeok Choi ,  Jong-Won Lee

IPC: H01L23/522

CPC classification number: H01L25/105 ,  H01L23/5386 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package includes a first substrate on which a first semiconductor chip is mounted, a second substrate spaced apart from the first substrate and on which a second semiconductor chip is mounted, first pads disposed on the first substrate, second pads disposed on the second substrate to be opposite to the first pads, and connection patterns electrically connecting the opposite first and second pads to each other, respectively. The first pads are disposed asymmetrically with respect to the central axis of the first substrate.

Abstract translation: 半导体封装包括：第一衬底，其上安装有第一半导体芯片;第二衬底，与第一衬底间隔开并且安装有第二半导体芯片;第一焊盘，设置在第一衬底上;第二焊盘，设置在第二衬底上; 与第一焊盘相对，以及将相对的第一焊盘和第二焊盘彼此电连接的连接图案。 第一衬垫相对于第一衬底的中心轴非对称地设置。

公开(公告)号：US08133611B2

公开(公告)日：2012-03-13

申请号：US12090292

申请日：2006-10-17

Applicant: Branko N. Popov ,  Jong-Won Lee

Inventor： Branko N. Popov ,  Jong-Won Lee

IPC: H01M4/04 ,  H01B1/12

CPC classification number: H01M4/54 ,  H01M4/06 ,  H01M4/364 ,  H01M4/382 ,  H01M4/60 ,  H01M4/606 ,  H01M6/16

Abstract: In one embodiment of the present disclosure, a composite electrode for a battery is provided. The composite electrode includes silver vanadium oxide present in an amount from about 75 weight percent to about 99 weight percent and polypyrrole present in an amount from about 1 weight percent to about 25 weight percent.

Abstract translation: 在本公开的一个实施例中，提供了一种用于电池的复合电极。 复合电极包括以约75重量％至约99重量％的量存在的银钒氧化物，并且存在量为约1重量％至约25重量％的聚吡咯。

公开(公告)号：US08130564B2

公开(公告)日：2012-03-06

申请号：US13217607

申请日：2011-08-25

Applicant: Jong Won Lee

Inventor： Jong Won Lee

IPC: G11C7/10

CPC classification number: G11C7/1045 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1063

Abstract: A semiconductor memory device is provided that is capable of reading out mode register information stored in a register adapted for LPDDR2 (Low Power DDR2), through DQ pads. The semiconductor memory device includes a mode register control unit configured to receive address signals, a mode register write signal and a mode register read signal and generate a flag signal and at least one output information signal, and a global I/O line latch unit for transferring the output information signal to a global I/O line in response to the flag signal.

Abstract translation: 提供半导体存储器件，其能够通过DQ焊盘读出存储在适合于LPDDR2（低功率DDR2）的寄存器中的模式寄存器信息。 半导体存储器件包括配置为接收地址信号的模式寄存器控制单元，模式寄存器写入信号和模式寄存器读取信号，并且生成标志信号和至少一个输出信息信号，以及全局I / O线锁存单元， 响应于标志信号将输出信息信号传送到全局I / O线。