公开(公告)号：US08248103B2

公开(公告)日：2012-08-21

申请号：US13043873

申请日：2011-03-09

申请人： Chang-Kyu Choi ,  Kyung-Hoon Kim

发明人： Chang-Kyu Choi ,  Kyung-Hoon Kim

IPC分类号： H03K19/0175

CPC分类号： H03K5/08 ,  H04L25/0264 ,  H04L25/028

摘要： An output circuit of a semiconductor device includes a signal selector configured to receive first and second input data signals and sequentially outputting the first and second input data signals in response to a phase signal; and an output level controller configured to control a voltage level of an output signal of the signal selector based on the first and second input data signals.

摘要翻译： 半导体器件的输出电路包括：信号选择器，被配置为接收第一和第二输入数据信号，并响应于相位信号顺序地输出第一和第二输入数据信号; 以及输出电平控制器，被配置为基于第一和第二输入数据信号来控制信号选择器的输出信号的电压电平。

公开(公告)号：US08194496B2

公开(公告)日：2012-06-05

申请号：US13105431

申请日：2011-05-11

申请人： Kyung-Hoon Kim ,  Sang-Yeon Byeon ,  Chang-Kyu Choi

发明人： Kyung-Hoon Kim ,  Sang-Yeon Byeon ,  Chang-Kyu Choi

IPC分类号： G11C8/18

CPC分类号： H03H11/26

摘要： Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus includes a plurality of signal receiving units configured to receive signals through a plurality of input/output pads and transfer the signals according to a receiving reference clock, the signal receiving units being divided into groups, a plurality of phase detection units configured to detect phases of signals output from the groups of the signal receiving units, a plurality of phase detection control units configured to control the phase detection units so that the phase detection units sequentially detect the phases of the signals output from each of the groups of the signal receiving units and a notification unit configured to output signals output from the phase detection units.

公开(公告)号：US08030981B2

公开(公告)日：2011-10-04

申请号：US12486320

申请日：2009-06-17

申请人： Kyung-Hoon Kim

发明人： Kyung-Hoon Kim

IPC分类号： H03H11/26

CPC分类号： H03L7/0814 ,  G11C7/1045 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C2207/2272

摘要： A semiconductor device includes a latency signal generating circuit for generating a latency signal corresponding CAS latency by measuring a delay amount reflected at a delay locked loop and reflecting the measured delay amount at a read command signal, and a delay locked loop for controlling an internal clock signal applied to the latency signal generating circuit corresponding to the read command and the latency signal. The semiconductor device includes an internal clock signal generating block configured to generate an internal clock signal, a latency generating block configured to generate a latency signal by synchronizing a read command signal with the internal clock signal at a time corresponding to a CAS latency value and a measured delay value, and an input controlling block configured to activate the reference clock signal using an external clock signal in response to the read command signal and the latency signal.

摘要翻译： 一种半导体器件包括等待时间信号发生电路，用于通过测量在延迟锁定环路处反映的延迟量并反映读取命令信号的测量延迟量来产生对应于CAS等待时间的等待时间信号，以及延迟锁定环路，用于控制内部时钟 信号被施加到对应于读命令和等待时间信号的等待时间信号发生电路。 半导体器件包括：内部时钟信号产生模块，用于产生内部时钟信号;等待时间产生模块，被配置为通过在与CAS等待时间值对应的时间同步读取命令信号和内部时钟信号来生成等待时间信号; 测量延迟值，以及输入控制块，被配置为响应于读取命令信号和等待时间信号，使用外部时钟信号激活参考时钟信号。

公开(公告)号：US20110227894A1

公开(公告)日：2011-09-22

申请号：US12946176

申请日：2010-11-15

申请人： Yang-Hwa Choi ,  Seung-Kyu Lee ,  Kyung-Hoon Kim ,  Chul-Ho Kim ,  Se-Hyang Kim

发明人： Yang-Hwa Choi ,  Seung-Kyu Lee ,  Kyung-Hoon Kim ,  Chul-Ho Kim ,  Se-Hyang Kim

IPC分类号： G06F3/038

CPC分类号： G09G3/3655 ,  G09G2300/0814 ,  G09G2310/0281 ,  G09G2320/0252 ,  G09G2330/021

摘要： A display device includes: a plurality of pixels; a data driver connected to the plurality of pixels by a plurality of data lines and applying data signals to the plurality of pixels; a scan driver connected to the plurality of pixels by a plurality of scan lines and applying scan signals to the plurality of pixels for the data signals to be applied to the plurality of pixels; a boost driver connected to the plurality of pixels by a plurality of boost lines and applying boost signals, boosting the pixel voltage charged to the plurality of pixels by the data signals, to the plurality of pixels; and a boost voltage maintaining unit applying a restoring voltage restoring the voltage in the plurality of boost lines by the scan signal to the plurality of boost lines. The voltage generated in the boost line by the coupling may be quickly restored and the crosstalk may be minimized, thereby improving the image quality.

摘要翻译： 显示装置包括：多个像素; 数据驱动器，其通过多条数据线连接到所述多个像素，并将数据信号施加到所述多个像素; 扫描驱动器，其通过多条扫描线连接到所述多个像素，并且将扫描信号施加到所述多个像素，以供应用于所述多个像素的数据信号; 升压驱动器，其通过多个升压线连接到所述多个像素，并且施加升压信号，通过所述数据信号将所述多个像素的像素电压升压到所述多个像素; 以及升压保持单元，通过所述扫描信号将多个升压线中的电压恢复到所述多个升压线路而施加恢复电压。 通过耦合在升压线中产生的电压可以被快速恢复，并且串扰可以被最小化，从而提高图像质量。

公开(公告)号：US20110210779A1

公开(公告)日：2011-09-01

申请号：US13105431

申请日：2011-05-11

申请人： KYUNG-HOON KIM ,  SANG-YEON BYEON ,  CHANG-KYU CHOI

发明人： KYUNG-HOON KIM ,  SANG-YEON BYEON ,  CHANG-KYU CHOI

IPC分类号： H03H11/26

CPC分类号： H03H11/26

摘要： Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus includes a plurality of signal receiving units configured to receive signals through a plurality of input/output pads and transfer the signals according to a receiving reference clock, the signal receiving units being divided into groups, a plurality of phase detection units configured to detect phases of signals output from the groups of the signal receiving units, a plurality of phase detection control units configured to control the phase detection units so that the phase detection units sequentially detect the phases of the signals output from each of the groups of the signal receiving units and a notification unit configured to output signals output from the phase detection units.

摘要翻译： 用于恢复高度集成的半导体存储装置中的时钟数据的电路和方法包括：多个信号接收单元，被配置为通过多个输入/输出焊盘接收信号，并根据接收的参考时钟传送信号，信号接收单元被分成 多个相位检测单元，被配置为检测从信号接收单元的组输出的信号的相位;多个相位检测控制单元，被配置为控制相位检测单元，使得相位检测单元顺序地检测相位检测单元的相位; 从信号接收单元的每个组输出的信号和被配置为输出从相位检测单元输出的信号的通知单元。

公开(公告)号：US20110187427A1

公开(公告)日：2011-08-04

申请号：US12751671

申请日：2010-03-31

申请人： Kyung-Hoon KIM ,  Kyung-Whan Kim

发明人： Kyung-Hoon KIM ,  Kyung-Whan Kim

IPC分类号： H03L7/06

CPC分类号： H03L7/06

摘要： A latency control circuit includes a delay unit configured to delay an input signal for a delay corresponding to a phase difference between an external clock and an internal clock and generate a delayed input signal, a delay information generation unit configured to generate a delay information based on a latency information and a delay amount of the input signal caused by a chip including the latency control circuit, a shift unit configured to shift the delayed input signal for a time period corresponding to the delay information in synchronism with the internal clock and an asynchronous control unit configured to selectively control the shift unit to output the delayed input signal without performing a shift operation.

摘要翻译： 延迟控制电路包括：延迟单元，被配置为延迟与外部时钟和内部时钟之间的相位差对应的延迟的输入信号，并生成延迟的输入信号;延迟信息生成单元，被配置为基于 延迟信息和由包括等待时间控制电路的芯片引起的输入信号的延迟量;移位单元，被配置为与延迟信号相对应的延迟输入信号与内部时钟同步地移位;异步控制 单元，被配置为选择性地控制所述移位单元以输出所述延迟的输入信号，而不执行移位操作。

公开(公告)号：US07983095B2

公开(公告)日：2011-07-19

申请号：US12345835

申请日：2008-12-30

申请人： Kyung Hoon Kim ,  Sang Sic Yoon ,  Hong Bae Kim

发明人： Kyung Hoon Kim ,  Sang Sic Yoon ,  Hong Bae Kim

IPC分类号： G11C7/10

CPC分类号： G11C7/1039 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1048

摘要： A semiconductor memory apparatus includes a first data selection section inputted with the first data and second data and output one of the first data and the second data as first selection data in response to an address signal, a second data selection section inputted with the second data and the first selection data and output one of the second data and the first selection data as second selection data depending upon an input and output mode, and a data output section configured to be inputted with the first and second selection data and output first and second output data.

摘要翻译： 半导体存储装置包括：第一数据选择部，输入第一数据和第二数据，并响应于地址信号输出第一数据和第二数据之一作为第一选择数据;第二数据选择部，输入第二数据 和第一选择数据，并且根据输入和输出模式将第二数据和第一选择数据中的一个作为第二选择数据输出，以及数据输出部分，被配置为输入第一和第二选择数据并输出第一和第二 输出数据。

公开(公告)号：US07961008B2

公开(公告)日：2011-06-14

申请号：US11647491

申请日：2006-12-29

申请人： Kyung-Hoon Kim ,  Tae-Heui Kwon

发明人： Kyung-Hoon Kim ,  Tae-Heui Kwon

IPC分类号： H03K19/094

CPC分类号： H03K19/0005

摘要： A data output driving circuit includes a plurality of driving units that are set to have different impedance values from one another, and the number of driving units is less than the number of a plurality of required driving impedance values such that the driving units can obtain the plurality of required driving impedance values by a combination thereof, and a driving control unit that independently controls the operation of the plurality of driving units so as to obtain the plurality of driving impedance values required.

摘要翻译： 数据输出驱动电路包括被设定为彼此具有不同阻抗值的多个驱动单元，并且驱动单元的数量小于多个要求的驱动阻抗值的数量，使得驱动单元可以获得 通过其组合的多个所需的驱动阻抗值，以及独立地控制多个驱动单元的操作以获得所需的多个驱动阻抗值的驱动控制单元。

公开(公告)号：US07889594B2

公开(公告)日：2011-02-15

申请号：US12327312

申请日：2008-12-03

申请人： Sang-Sic Yoon ,  Kyung-Hoon Kim

发明人： Sang-Sic Yoon ,  Kyung-Hoon Kim

IPC分类号： G11C11/00

CPC分类号： G11C8/18 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

摘要： A circuit which can reduce time taken by a clock alignment training operation in a semiconductor memory device is provided. The semiconductor memory device, which includes: a clock inputting unit configured to receive a system clock and a data clock; a clock dividing unit configured to divide a frequency of the data clock to generate a data division clock, wherein the clock dividing unit determines a phase of the data division clock in response to an inversion division control signal; a phase dividing unit configured to generate a plurality of multiple phase data division clocks having respective predetermined phase differences in response to the data division clock; a data serializing unit configured to serialize predetermined parallel pattern data in correspondence with the multiple phase data division clocks; and a signal transmitting unit configured to transmit an output signal of the data serializing unit to the outside.

摘要翻译： 提供一种可以减少半导体存储器件中的时钟对准训练操作所花费的时间的电路。 所述半导体存储器件包括：时钟输入单元，被配置为接收系统时钟和数据时钟; 时钟分频单元，被配置为分频数据时钟的频率以产生数据分时钟，其中所述时钟分频单元响应于反相分配控制信号确定所述数据分时钟的相位; 相位分割单元，被配置为响应于所述数据分时钟产生具有相应的预定相位差的多个多相数据分时钟; 数据串行化单元，被配置为与多个相位数据分时钟对应地串行化预定的并行模式数据; 以及信号发送单元，被配置为将数据串行化单元的输出信号发送到外部。

公开(公告)号：US07881148B2

公开(公告)日：2011-02-01

申请号：US12277650

申请日：2008-11-25

申请人： Kyung-Hoon Kim ,  Sang-Sic Yoon ,  Hong-Bae Kim

发明人： Kyung-Hoon Kim ,  Sang-Sic Yoon ,  Hong-Bae Kim

IPC分类号： G11C8/00 ,  G11C8/18 ,  H03K3/017

CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C7/225

摘要： A semiconductor memory device includes a clock supply portion for providing an external clock to the interior of the memory device, a clock transfer portion for transferring the clock from the clock supply portion to each of elements in the memory device and data output portions for outputting data in synchronism the clock from the clock transfer portion, wherein the clock from the clock supply portion to the clock transfer portion swings at a current mode logic (CML) level.

摘要翻译： 一种半导体存储器件，包括用于向存储器件内部提供外部时钟的时钟提供部分，用于将时钟从时钟供应部分传送到存储器件中的每个元件的时钟传送部分和用于输出数据的数据输出部分 同步来自时钟传送部分的时钟，其中从时钟提供部分到时钟传送部分的时钟以当前模式逻辑（CML）电平摆动。