Snubber circuit for buck converter
    111.
    发明授权
    Snubber circuit for buck converter 失效
    降压转换器的缓冲电路

    公开(公告)号:US08513931B2

    公开(公告)日:2013-08-20

    申请号:US13031621

    申请日:2011-02-22

    CPC classification number: H02M3/155 H02M2001/344

    Abstract: A snubber circuit for decreasing a voltage spike of a buck converter includes a resistor unit, a capacitor unit, a detecting unit, and a control unit. The resistor unit provides multiple groups of resistance values. The capacitor unit provides multiple groups of capacitance values. The detecting unit detects voltage spikes of the buck converter corresponding to each group of resistance values and capacitance values. The control unit selects each group of resistance and capacitance to respectively connect to the buck converter and determines a group of resistance and capacitance corresponding to a lowest voltage spike by comparing the detected voltage spikes with each other.

    Abstract translation: 用于降低降压转换器的电压尖峰的缓冲电路包括电阻单元,电容器单元,检测单元和控制单元。 电阻单元提供多组电阻值。 电容器单元提供多组电容值。 检测单元检测对应于每组电阻值和电容值的降压转换器的电压尖峰。 控制单元选择每组电阻和电容分别连接到降压转换器,并通过将检测到的电压尖峰相互比较来确定与最低电压尖峰相对应的一组电阻和电容。

    System and method for accelerated network entrance
    112.
    发明授权
    System and method for accelerated network entrance 有权
    加速网络入口的系统和方法

    公开(公告)号:US08400963B2

    公开(公告)日:2013-03-19

    申请号:US12562190

    申请日:2009-09-18

    Abstract: In one embodiment, a method for wireless communication includes providing, at a base station, access to a network to a preferred endpoint during a first communication session. In addition, the method includes determining, at the base station, to treat the preferred endpoint as preferred. The method also includes causing, at the base station, at least one parameter regarding the preferred endpoint used to establish the first communication session to be stored in response to determining to treat the preferred endpoint as preferred. In addition, the method includes receiving, at the base station, a request for a second communication session after the first communication session has ended. Further, the method includes determining, at the base station, that the request for the second communication session was sent by the preferred endpoint. The method also includes retrieving, at the base station, the stored at least one parameter in response to determining that the preferred endpoint sent the request for the second communication session. Moreover, the method includes utilizing, at the base station, the retrieved at least one parameter to establish the second communication session with the preferred endpoint. The method also includes providing, at the base station, access to the network to the preferred endpoint during the second communication session.

    Abstract translation: 在一个实施例中,一种用于无线通信的方法包括在第一通信会话期间在基站向第一终端提供对网络的访问。 另外,该方法包括在基站处确定优选端点来处理优选端点。 该方法还包括在基站处,响应于确定将优选端点视为优选,在基站处引起关于用于建立要存储的第一通信会话的优选端点的至少一个参数。 此外,该方法包括在第一通信会话结束之后在基站处接收对第二通信会话的请求。 此外,该方法包括在基站处确定由优选端点发送对第二通信会话的请求。 该方法还包括响应于确定优选端点向第二通信会话发送请求而在基站处检索存储的至少一个参数。 此外,该方法包括在基站处利用所检索的至少一个参数来建立与优选端点的第二通信会话。 该方法还包括在第二通信会话期间在基站处向最优端点提供对网络的访问。

    Asynchronous first in first out interface, method thereof and integrated receiver
    114.
    发明授权
    Asynchronous first in first out interface, method thereof and integrated receiver 有权
    先进先出的接口及其接收方法

    公开(公告)号:US08346201B2

    公开(公告)日:2013-01-01

    申请号:US12763281

    申请日:2010-04-20

    Applicant: Tse-Peng Chen

    Inventor: Tse-Peng Chen

    Abstract: An asynchronous FIFO interface having a readout clock asynchronous with a write clock is provided. The asynchronous FIFO interface includes a FIFO buffer, a clock controller, a reference source and a signal source. The FIFO buffer receives a digital signal from an ADC according to the write clock and outputs a digital signal to a processor according to the readout clock. The clock controller outputs a clock control signal according to the amount of data stored in the FIFO buffer. The reference source provides an oscillation frequency. The signal source divides the oscillation frequency by a first integer divisor to generate a reference frequency, divides the readout clock by a second integer divisor to generate an input frequency, and outputs a control signal by comparing the reference frequency with the input frequency.

    Abstract translation: 提供了具有与写时钟异步的读出时钟的异步FIFO接口。 异步FIFO接口包括FIFO缓冲器,时钟控制器,参考源和信号源。 FIFO缓冲器根据写时钟从ADC接收数字信号,并根据读出时钟将数字信号输出到处理器。 时钟控制器根据存储在FIFO缓冲器中的数据量输出时钟控制信号。 参考源提供振荡频率。 信号源将振荡频率除以第一整数除数以产生参考频率,将读出时钟除以第二整数除数以产生输入频率,并通过将参考频率与输入频率进行比较来输出控制信号。

    Output voltage adjustment circuit for buck circuits
    115.
    发明授权
    Output voltage adjustment circuit for buck circuits 失效
    降压电路的输出电压调整电路

    公开(公告)号:US08339119B2

    公开(公告)日:2012-12-25

    申请号:US13073980

    申请日:2011-03-28

    CPC classification number: H02M3/157 H02M2001/0025

    Abstract: An output voltage adjustment circuit for buck circuits includes a microcontroller, first to eighth keys, and a display unit. The first to eighth keys input voltage adjustment signals to the microcontroller. A first input pin of the microcontroller is connected to a voltage output terminal. A second resistor is connected between the first input pin of the microcontroller and ground. A first to a sixth input/output pin of the microcontroller are connected to the display unit. A first to an eighth output pin of the microcontroller are connected to a pulse width modulation (PWM) controller. The first to eighth keys are selectively activated to provide voltage adjustment signals to the microcontroller, sampling output voltages of the voltage output terminal, comparing with a predetermined voltage, controlling the PWM controller to fine tune the duty cycle to output a stable voltage from the voltage output terminal. The display unit displays the voltages on the voltage output terminal.

    Abstract translation: 用于降压电路的输出电压调节电路包括微控制器,第一至第八键和显示单元。 第一至第八键输入电压调节信号给微控制器。 微控制器的第一个输入引脚连接到电压输出端子。 第二个电阻连接在微控制器的第一个输入引脚和地之间。 微控制器的第一至第六输入/输出引脚连接到显示单元。 微控制器的第一至第八输出引脚连接到脉宽调制(PWM)控制器。 选择性地激活第一至第八键以向微控制器提供电压调整信号,与预定电压相比较,对电压输出端子的输出电压进行采样,控制PWM控制器以微调占空比以从电压输出稳定的电压 输出端子。 显示单元显示电压输出端子上的电压。

    System and Method for Managing Power Consumption
    116.
    发明申请
    System and Method for Managing Power Consumption 有权
    管理功耗的系统和方法

    公开(公告)号:US20120316687A1

    公开(公告)日:2012-12-13

    申请号:US13372592

    申请日:2012-02-14

    Abstract: In accordance with a particular embodiment, a method for managing power consumption includes receiving power rate information and receiving power usage information. The method also includes receiving a plurality of personal preference profiles. Each personal preference profile of the plurality of personal preference profiles is associated with a different user of a plurality of users and includes at least one preferred state associated with a respective user. The method further includes detecting a presence of at least one user within a room. The method additionally includes adjusting at least one state associated with the room based on the at least one preferred state associated with the at least one user within the room, the power rate information, and the power usage information.

    Abstract translation: 根据特定实施例,一种用于管理功耗的方法包括接收功率速率信息和接收功率使用信息。 该方法还包括接收多个个人偏好简档。 多个个人偏好简档的每个个人偏好简档与多个用户的不同用户相关联,并且包括与相应用户相关联的至少一个优选状态。 该方法还包括检测房间内至少一个用户的存在。 该方法还包括基于与房间内的至少一个用户相关联的至少一个优选状态,功率速率信息和功率使用信息来调整与房间相关联的至少一个状态。

    SEQUENCE CONTROL CIRCUIT FOR POWER SOURCE
    117.
    发明申请
    SEQUENCE CONTROL CIRCUIT FOR POWER SOURCE 有权
    电源序列控制电路

    公开(公告)号:US20120306273A1

    公开(公告)日:2012-12-06

    申请号:US13181523

    申请日:2011-07-13

    Abstract: A sequence control circuit for power sources includes two switched circuits and a sequence control unit. Each of the switched circuits has a control node and is coupled between a power source and a load. The sequence control unit includes two output terminals coupled to the control nodes. The output terminals generate control signals to control the sequence of the circuits being turned on.

    Abstract translation: 用于电源的序列控制电路包括两个开关电路和一个序列控制单元。 每个开关电路具有控制节点并耦合在电源和负载之间。 序列控制单元包括耦合到控制节点的两个输出端。 输出端产生控制信号以控制电路接通的顺序。

    JIG FOR SURFACE TREATMENT
    118.
    发明申请
    JIG FOR SURFACE TREATMENT 有权
    JIG表面处理

    公开(公告)号:US20120299231A1

    公开(公告)日:2012-11-29

    申请号:US13472847

    申请日:2012-05-16

    CPC classification number: C25D17/06 C25D17/08

    Abstract: The present disclosure provides a jig for surface treatment, which is used for fixing a metal plate having a bearing for surface treatment. The jig for surface treatment according to the present disclosure passes a hanging rod through the metal plate. Thereby, the jig for surface treatment will not contact with a processed surface of the metal plate and hence making no apparent flaws on the processed surface and maintaining completeness processed surface. In addition, the jig for surface treatment can load a plurality of metal plates at a time, performing surface treatment on the plurality of metal plates simultaneously, and thus improving productivity and practicability.

    Abstract translation: 本公开提供了一种用于表面处理的夹具,其用于固定具有用于表面处理的轴承的金属板。 根据本公开的用于表面处理的夹具通过悬挂杆穿过金属板。 因此,用于表面处理的夹具不会与金属板的加工表面接触,因此在加工表面上没有明显的缺陷并保持完整的加工表面。 此外,用于表面处理的夹具可以一次加载多个金属板,同时对多个金属板进行表面处理,从而提高生产率和实用性。

    Driver circuit
    119.
    发明授权
    Driver circuit 失效
    驱动电路

    公开(公告)号:US08314640B2

    公开(公告)日:2012-11-20

    申请号:US13110917

    申请日:2011-05-19

    CPC classification number: G06F1/26

    Abstract: A driver circuit drives a pulse width modulation (PWM) controller. The driver circuit includes an enabling circuit, a power supply input control circuit, a stabilizing circuit, and a discharge circuit. The stabilizing circuit is electrically connected to the PWM controller. The power supply input control circuit is electrically connected between the enabling circuit and the stabilizing circuit. The discharge circuit is electrically connected between the stabilizing circuit and the ground. In response to the driver circuit working in normal operation, the enabling circuit enables the power supply input control circuit to output a working voltage to the stabilizing circuit, and in response to the process of the driver circuit restarting, the enabling circuit enables the power supply input to stop outputting power supply to the stabilizing circuit. The discharge circuit leads a residual voltage of the stabilizing circuit to the ground, during the process of the driver circuit being restarted.

    Abstract translation: 驱动电路驱动脉宽调制(PWM)控制器。 驱动器电路包括使能电路,电源输入控制电路,稳定电路和放电电路。 稳压电路与PWM控制器电连接。 电源输入控制电路电连接在使能电路和稳定电路之间。 放电电路电连接在稳压电路和地之间。 响应于驱动电路正常工作,使能电路使得电源输入控制电路向稳定电路输出工作电压,并且响应于驱动电路重新启动的过程,使能电路使电源 输入停止向稳定电路输出电源。 在驱动器电路重新启动的过程中,放电电路将稳定电路的剩余电压引向地。

    Initialization of reference signal scrambling
    120.
    发明授权
    Initialization of reference signal scrambling 有权
    参考信号加扰初始化

    公开(公告)号:US08300587B2

    公开(公告)日:2012-10-30

    申请号:US12715353

    申请日:2010-03-01

    CPC classification number: H04J11/0069 H04L27/2613

    Abstract: A scrambling sequence is initialized using at least a cell identifier and an offset, and a physical downlink control information DCI is sent to a user equipment which indicates the offset. In more particular embodiments a user equipment-specific reference signal UE-RS is scrambled using the initialized scrambling sequence, and the scrambled UE-RS is sent to the UE for demodulating a downlink shared channel (PDSCH). In another exemplary embodiment the generated UE-RS is sent in a pilot part of a subframe transmission associated with the PDSCH and is for demodulating at least a data part of that subframe transmission. In a specific embodiment from the UE side, the UE receives the UE-RS and the DCI which indicates the offset, descrambles the UE-RS using a scrambling sequence that is initialized using a cell identifier and the indicated offset; and demodulates the PDSCH using the de-scrambled UE-RS.

    Abstract translation: 使用至少小区标识符和偏移来初始化加扰序列,并且向指示偏移的用户设备发送物理下行链路控制信息DCI。 在更具体的实施例中,使用初始化的加扰序列对用户设备专用参考信号UE-RS进行加扰,并且将加扰的UE-RS发送给用于解调下行链路共享信道(PDSCH)的UE。 在另一个示例性实施例中,所生成的UE-RS在与PDSCH相关联的子帧传输的导频部分中被发送,并且用于解调该子帧传输的至少一个数据部分。 在来自UE侧的特定实施例中,UE接收指示偏移的UE-RS和DCI,使用使用小区标识符和指示的偏移量初始化的加扰序列来解扰UE-RS; 并使用去加扰的UE-RS解调PDSCH。

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