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公开(公告)号：US12259844B2
公开(公告)日：2025-03-25
申请号：US17829902
申请日：2022-06-01
Inventor： Giuseppe Cavallaro , Fred Rennig
IPC: G06F13/42 , G05B19/042 , G06F11/10 , G06F13/38 , G06F13/40
Abstract: In an embodiment a microcontroller includes a processing unit and a deserial-serial peripheral interface (DSPI) module, wherein the deserial-serial peripheral interface module is coupleable to a communication bus configured to operate according to a selected communication protocol, wherein the processing unit is configured to read user data intended for inclusion in an outgoing frame encoded according to the selected communication protocol, calculate, as a function of the user data, a cyclic redundancy check (CRC) value intended for inclusion in the outgoing frame, compose the outgoing frame by including the user data and the calculated CRC value into the outgoing frame, produce a DSPI frame encoded according to the selected communication protocol as a function of the outgoing frame and program a data register of the deserial-serial peripheral interface module with the DSPI frame, and wherein the deserial-serial peripheral interface module is configured to transmit the DSPI frame via the communication bus.
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公开(公告)号：US12210609B2
公开(公告)日：2025-01-28
申请号：US17515149
申请日：2021-10-29
Inventor： Avneep Kumar Goyal , Thomas Szurmant
Abstract: A system on a chip including a first-port controller for a first development port configured to receive a first development tool and a second-port controller for a second development port configured to receive a second development tool. The system on a chip further including a central controller in communication with the first-port controller, the second-port controller, and a security subsystem. The central controller being configured to manage authentication exchanges between the security subsystem and the first development tool and authentication exchanges between the security subsystem and the second development tool.
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公开(公告)号：US12147209B2
公开(公告)日：2024-11-19
申请号：US17704675
申请日：2022-03-25
Inventor： Rosario Martorana , Mose' Alessandro Pernice , Roberto Colombo
IPC: G05B19/042
Abstract: A set of configuration memory locations store configuration data for a microcontroller unit. A hardware monitoring module is coupled by an interconnection bus to the configuration memory locations. The hardware monitoring module reads from an instruction memory a command including an address of a target memory location in the set of configuration memory locations. Data is read from the target memory location corresponding to the address read and a checksum value is computed as a function of the data that is read from the target memory location. The computed checksum value is then compared to a respective expected checksum value stored in a checksum storage unit. An alarm signal is triggered in response to a mismatch detected between the computed checksum value and the respective expected checksum value.
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114.发明公开公开(公告)号：US20240362176A1
公开(公告)日：2024-10-31
申请号：US18764940
申请日：2024-07-05
Inventor： Fred Rennig , Ludek Beran
IPC: G06F13/362 , G05B19/042 , G06F9/54 , G06F11/07 , G06F11/10 , G06F13/40 , G06F13/42 , H03M13/09 , H04L12/40 , H04L12/403
CPC classification number: G06F13/362 , G05B19/042 , G06F9/542 , G06F11/0739 , G06F11/0757 , G06F11/0772 , G06F11/1004 , G06F13/4068 , G06F13/4282 , H04L12/40006 , H04L12/40013 , H04L12/40078 , H04L12/403 , G05B2219/1215 , G05B2219/2231 , G05B2219/31179 , H03M13/09 , H04L2012/40215
Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.
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公开(公告)号：US12118376B2
公开(公告)日：2024-10-15
申请号：US17235206
申请日：2021-04-20
Inventor： Deepak Baranwal , Amritanshu Anand , Roberto Colombo , Boris Vittorelli
CPC classification number: G06F9/45558 , G06F9/455 , G06F9/45533 , G06F9/48 , G06F9/4812 , G06F9/4843 , G06F9/485 , G06F9/4856 , G06F9/4881 , G06F9/50 , G06F9/5083 , G06F9/5088 , G06F2009/4557 , G06F2009/45575
Abstract: Disclosed herein is hardware for easing the process of changing the execution mode of a virtual machine and its associated resources. By adopting the hardware, it is possible to trigger a change in the execution mode in an automatic way, without software intervention, and without interfering with the execution of other virtual machines. In addition, in case an error has occurred for a virtual machine and it is detected, the hardware can be used to disable the resources associated with that virtual machine and generate notification of the completion this operation to other hardware, which will complete the reset of the virtual machine. By adopting the hardware, the execution mode change is simplified and offers configurability and flexibility for a system running multiple virtual machines.
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Patent Agency Ranking
公开(公告)号：US12068057B2
公开(公告)日：2024-08-20
申请号：US18056803
申请日：2022-11-18
Applicant: STMicroelectronics S.r.l. , STMicroelectronics International N.V. , STMicroelectronics Application GMBH
Inventor： Asif Rashid Zargar , Nicolas Bernard Grossier , Charul Jain , Roberto Colombo
CPC classification number: G11C7/24 , G11C7/1039 , G11C7/1069
Abstract: In an embodiment a processing system includes a plurality of storage elements, each storage element comprising a latch or a flip-flop and being configured to receive a write request comprising a data bit and to store the received data bit to the latch or the flip-flop, a non-volatile memory configured to store data bits for the plurality of storage elements, a hardware configuration circuit configured to read the data bits from the non-volatile memory and generate write requests in order to store the data bits to the storage elements and a hardware circuit configured to change operation as a function of a logic level stored to a latch or a flip-flop of a first storage element of the plurality of storage elements, wherein the first storage element comprises a further latch or a further flip-flop and is configured to store, in response to the write request, an inverted version of the received data bit to the further latch or the further flip-flop.
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公开(公告)号：US12068048B2
公开(公告)日：2024-08-20
申请号：US17815807
申请日：2022-07-28
Inventor： Vivek Mohan Sharma , Roberto Colombo
CPC classification number: G11C29/42 , G11C29/36 , G11C29/48 , G11C2029/3602
Abstract: A processing system includes an error detection circuit configured to receive data bits and ECC bits, calculate further ECC bits as a function of the data bits, and generate a syndrome by comparing the calculated ECC bits with the received ECC bits. When the syndrome corresponds to one of N+K single bit-flip reference syndromes, the error detection circuit asserts a first error signal, and asserts one bit of a bit-flip signature corresponding to a single bit-flip error indicated by the respective single bit-flip reference syndrome.
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公开(公告)号：US12019118B2
公开(公告)日：2024-06-25
申请号：US18186549
申请日：2023-03-20
Inventor： Roberto Colombo , Vivek Mohan Sharma , Samiksha Agarwal
IPC: G01R31/317
CPC classification number: G01R31/31703 , G01R31/31722
Abstract: In an embodiment a processing system includes a test circuit configured to set an address value, an upper address limit and a lower address limit to a given reference bit sequence, verify whether the upper-limit comparison signal has a respective third logic level and/or whether the lower-limit comparison signal has the respective third logic level, assert an error signal in response to determining that the upper-limit comparison signal does not have the respective third logic level or the lower-limit comparison signal does not have the respective third logic level, repeat a certain operation for each of the N bits.
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公开(公告)号：US20230409341A1
公开(公告)日：2023-12-21
申请号：US18312237
申请日：2023-05-04
Inventor： Asif Rashid Zargar , Roberto Colombo
IPC: G06F9/4401 , G06F21/64
CPC classification number: G06F9/4405 , G06F21/64
Abstract: In embodiments, a reset management circuit executes reset, configuration, and software runtime phases when a processing system is switched on, where one or more microprocessors start at respective start addresses. During the configuration phase, a circuit reads a boot record from a non-volatile memory and stores it to registers. The circuit sequentially reads data records of configuration data from the non-volatile memory and generates a write request for each data record to store the data of the respective data record to a second circuit with associated address data indicated in the respective data record. The processing system processes the boot record and boot configuration data provided by the second circuits to selectively start a predetermined microprocessor at a default start address or at a start address indicated by the boot configuration data, or start one or more microprocessors at respective start addresses as indicated by the boot record.
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公开(公告)号：US20230385215A1
公开(公告)日：2023-11-30
申请号：US18364786
申请日：2023-08-03
Applicant: STMicroelectronics Application GMBH
Inventor： Rolf Nandlinger , Roberto Colombo
CPC classification number: G06F13/28 , G06F9/30105 , G06F21/72 , G06F13/4282 , G06F21/602 , G06F9/3877
Abstract: In an embodiment, a processing system comprises a microprocessor programmable via software instructions, a memory controller configured to be coupled to a memory, a communication system coupling the microprocessors to the memory controller, a cryptographic co-processor and a first communication interface. The processing system also comprises first and second configurable DMA channels. In a first configuration, the first DMA channel is configured to transfer data from the memory to the cryptographic co-processor, and the second DMA channel is configured to transfer the encrypted data via two loops from the cryptographic co-processor to the first communication interface. In a second configuration, the second DMA channel is configured to transfer received data via two loops from the first communication interface to the cryptographic co-processor, and the first DMA channel is configured to transfer the decrypted data from the cryptographic co-processor to the memory.
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