公开(公告)号：US20070224757A1

公开(公告)日：2007-09-27

申请号：US11756927

申请日：2007-06-01

申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Geng Wang

发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Geng Wang

IPC分类号： H01L21/8242

CPC分类号： H01L27/10867 ,  H01L27/1087 ,  H01L29/66181 ,  H01L29/945

摘要： The present invention includes a method for forming a memory array and the memory array produced therefrom. Specifically, the memory array includes at least one first-type memory device, each of the at least one first-type memory device comprising a first transistor and a first underlying capacitor that are in electrical contact to each other through a first buried strap, where the first buried strap positioned on a first collar region; and at least one second-type memory cell, where each of the at least are second-type memory device comprises a second transistor and a second underlying capacitor that are in electrical contact through an offset buried strap, where the offset buried strap is positioned on a second collar region, wherein the second collar region has a length equal to the first collar region.

摘要翻译： 本发明包括一种用于形成存储器阵列的方法和由其制成的存储器阵列。 具体而言，存储器阵列包括至少一个第一型存储器件，至少一个第一型存储器件中的每一个包括通过第一掩埋带彼此电接触的第一晶体管和第一底层电容器，其中 位于第一环区的第一掩埋带; 以及至少一个第二类型存储单元，其中至少第二类型存储器件中的每一个包括第二晶体管和第二底层电容器，所述第二晶体管和第二底层电容器通过偏移掩埋带电接触，其中所述偏移掩埋带位于 第二衣领区域，其中第二衣领区域具有等于第一衣领区域的长度。

公开(公告)号：US08222154B2

公开(公告)日：2012-07-17

申请号：US12368561

申请日：2009-02-10

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Geng Wang

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Geng Wang

IPC分类号： H01L21/302

CPC分类号： H01L21/0338 ,  H01L21/0337 ,  H01L21/26586 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/32134 ,  H01L21/32135 ,  H01L29/66795 ,  Y10S438/942 ,  Y10S438/947

摘要： A semiconductor device is formed by providing a substrate and forming a semiconductor-containing layer atop the substrate. A mask having a plurality of openings is then formed atop the semiconductor-containing layer, wherein adjacent openings of the plurality of openings of the mask are separated by a minimum feature dimension. Thereafter, an angled ion implantation is performed to introduce dopants to a first portion of the semiconductor-containing layer, wherein a remaining portion that is substantially free of dopants is present beneath the mask. The first portion of the semiconductor-containing layer containing the dopants is removed selective to the remaining portion of semiconductor-containing layer that is substantially free of the dopants to provide a pattern of sublithographic dimension, and the pattern is transferred into the substrate to provide a fin structure of sublithographic dimension.

摘要翻译： 通过提供衬底并在衬底上形成含半导体的层来形成半导体器件。 然后在半导体含有层顶上形成具有多个开口的掩模，其中掩模的多个开口中的相邻开口被最小特征尺寸分开。 此后，进行成角度的离子注入以将掺杂剂引入到半导体含有层的第一部分，其中基本上不含掺杂剂的剩余部分存在于掩模下方。 含有掺杂剂的含半导体层的第一部分被选择性地除去基本上不含掺杂剂的半导体含有层的剩余部分，以提供亚光刻尺寸的图案，并且将图案转移到衬底中以提供 翅片结构的亚光刻尺寸。

公开(公告)号：US20090174031A1

公开(公告)日：2009-07-09

申请号：US11969986

申请日：2008-01-07

申请人： Geng Wang ,  Kangguo Cheng ,  Johnathan E. Faltermeier ,  Paul C. Parries

发明人： Geng Wang ,  Kangguo Cheng ,  Johnathan E. Faltermeier ,  Paul C. Parries

IPC分类号： H01L29/92 ,  H01L21/28 ,  G06F17/50

CPC分类号： H01L29/66181 ,  G11C11/404 ,  H01L27/0805 ,  H01L27/10861

摘要： By controlling buried plate doping level and bias condition, different capacitances can be obtained from capacitors on the same chip with the same layout and deep trench process. The capacitors may be storage capacitors of DRAM/eDRAM cells. The doping concentration may be less than 3E19cm−3, a voltage difference between the biases of the buried electrodes may be at least 0.5V, and a capacitance of one capacitor may be at least 1.2 times, such as 2.0 times the capacitance of another capacitor.

摘要翻译： 通过控制掩埋板掺杂水平和偏置条件，可以在相同芯片上的电容器中获得不同的电容，具有相同的布局和深沟槽工艺。 电容器可以是DRAM / eDRAM单元的存储电容器。 掺杂浓度可以小于3E19cm-3，掩埋电极的偏压之间的电压差可以至少为0.5V，并且一个电容器的电容可以是至少1.2倍，例如另一个电容器的电容的2.0倍 。

公开(公告)号：US20090108356A1

公开(公告)日：2009-04-30

申请号：US11924053

申请日：2007-10-25

申请人： Kangguo Cheng ,  Michael P. Chudzik ,  Rama Divakaruni ,  Geng Wang ,  Robert C. Wong ,  Haining S. Yang

发明人： Kangguo Cheng ,  Michael P. Chudzik ,  Rama Divakaruni ,  Geng Wang ,  Robert C. Wong ,  Haining S. Yang

IPC分类号： H01L29/78 ,  H01L21/44

CPC分类号： H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1116 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

摘要： A metal gate stack containing a metal layer having a mid-band-gap work function is formed on a high-k gate dielectric layer. A threshold voltage adjustment oxide layer is formed over a portion of the high-k gate dielectric layer to provide devices having a work function near a first band gap edge, while another portion of the high-k dielectric layer remains free of the threshold voltage adjustment oxide layer. A gate stack containing a semiconductor oxide based gate dielectric and a doped polycrystalline semiconductor material may also be formed to provide a gate stack having a yet another work function located near a second band gap edge which is the opposite of the first band gap edge. A dense circuit containing transistors of p-type and n-type with the mid-band-gap work function are formed in the region containing the threshold voltage adjustment oxide layer.

摘要翻译： 在高k栅极电介质层上形成包含具有中带隙功函数的金属层的金属栅极堆叠。 在高k栅介质层的一部分上形成阈值电压调整氧化物层，以提供在第一带隙边缘附近具有功函数的器件，而高k电介质层的另一部分保持没有阈值电压调整 氧化层。 还可以形成包含半导体氧化物基栅极电介质和掺杂多晶半导体材料的栅极堆叠，以提供具有位于与第一带隙边缘相反的第二带隙边缘附近的又一功能功能的栅极堆叠。 在包含阈值电压调整氧化物层的区域中形成包含具有中带功函数的p型和n型晶体管的密集电路。

公开(公告)号：US20090047756A1

公开(公告)日：2009-02-19

申请号：US12254960

申请日：2008-10-21

申请人： Jack A. Mandelman ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Geng Wang

发明人： Jack A. Mandelman ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Geng Wang

IPC分类号： H01L21/84 ,  H01L21/8242

CPC分类号： H01L27/108 ,  H01L27/10829 ,  H01L27/10867 ,  H01L27/1203

摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.

摘要翻译： 使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。 具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。 各种增益单元布局在本领域中是已知的。 本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。 通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

公开(公告)号：US07459743B2

公开(公告)日：2008-12-02

申请号：US11161962

申请日：2005-08-24

申请人： Jack A. Mandelman ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Geng Wang

发明人： Jack A. Mandelman ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Geng Wang

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/108 ,  H01L27/10829 ,  H01L27/10867 ,  H01L27/1203

摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.

摘要翻译： 使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。 具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。 各种增益单元布局在本领域中是已知的。 本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。 通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

公开(公告)号：US20080185680A1

公开(公告)日：2008-08-07

申请号：US11306718

申请日：2006-01-09

申请人： Kangguo Cheng ,  Geng Wang

发明人： Kangguo Cheng ,  Geng Wang

IPC分类号： H01L21/8242 ,  H01L29/00

CPC分类号： H01L29/66181 ,  H01L27/0207 ,  H01L27/0805 ,  H01L27/1087

摘要： A method for manufacturing a device includes forming trenches of different morphologies into a substrate. At the upper surfaces, the trenches have different orientations with respect to each other. In an aspect, windows for the trenches are aligned along the and directions of a silicon substrate. The trenches of different morphologies may be formed into capacitors having different capacitance levels. Also included are devices prepared by the method.

摘要翻译： 一种制造器件的方法包括将不同形态的沟槽形成衬底。 在上表面，沟槽具有相对于彼此的不同取向。 在一个方面，用于沟槽的窗口沿着硅衬底的<100>和<110>方向排列。 不同形态的沟槽可以形成为具有不同电容电平的电容器。 还包括通过该方法制备的装置。

公开(公告)号：US20070296012A1

公开(公告)日：2007-12-27

申请号：US11853045

申请日：2007-09-11

申请人： Kangguo Cheng ,  Geng Wang

发明人： Kangguo Cheng ,  Geng Wang

IPC分类号： H01L27/108

CPC分类号： H01L22/34 ,  H01L27/1087 ,  H01L29/8605 ,  H01L2924/0002 ,  H01L2924/00

摘要： A test structure for implementing resistance measurement of a deep trench formed in a semiconductor device includes a deep trench formed within a semiconductor substrate. The deep trench has a dielectric material formed on upper portions of sidewall surfaces thereof, and includes a conductive fill material therein. A doped buried plate region encompasses a bottom portion of the deep trench, and a doped horizontal n-well band is in electrical contact with an upper portion of the doped buried plate region. A doped vertical n-well band is in electrical contact with the doped horizontal n-well band.

摘要翻译： 用于实现在半导体器件中形成的深沟槽的电阻测量的测试结构包括形成在半导体衬底内的深沟槽。 深沟槽具有形成在其侧壁表面的上部的介电材料，并且其中包括导电填充材料。 掺杂掩埋板区域包围深沟槽的底部，并且掺杂的水平n阱带与掺杂掩埋板区域的上部电接触。 掺杂的垂直n阱带与掺杂的水平n阱带电接触。

公开(公告)号：US08227310B2

公开(公告)日：2012-07-24

申请号：US12186780

申请日：2008-08-06

申请人： John E. Barth, Jr. ,  Kangguo Cheng ,  Michael Sperling ,  Geng Wang

发明人： John E. Barth, Jr. ,  Kangguo Cheng ,  Michael Sperling ,  Geng Wang

IPC分类号： H01L21/8242

CPC分类号： H01L21/76895 ,  H01L23/485 ,  H01L27/10867 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming an integrated circuit comprises: providing a semiconductor topography comprising an active transistor laterally adjacent to a trench capacitor formed in a semiconductor substrate, the active transistor comprising a source junction and a drain junction, wherein a barrier layer is disposed along a periphery of the trench capacitor for isolating the trench capacitor; forming an interlevel dielectric across the semiconductor topography; concurrently etching (i) a first opening through the interlevel dielectric to the drain junction of the active transistor and the trench capacitor, and (ii) a second opening through the interlevel dielectric to the source junction of the active transistor; and filling the first opening and the second opening with a conductive material to form a strap for electrically connecting the trench capacitor to the drain junction of the active transistor and to also form a contact for electrically connecting the source junction to an overlying level of the integrated circuit.

摘要翻译： 一种形成集成电路的方法包括：提供半导体形貌，其包括与形成在半导体衬底中的沟槽电容器横向相邻的有源晶体管，所述有源晶体管包括源极结和漏极结，其中阻挡层沿着外围设置 用于隔离沟槽电容器的沟槽电容器; 在半导体形貌上形成层间电介质; 同时蚀刻（i）通过层间电介质到有源晶体管和沟槽电容器的漏极结的第一开口，以及（ii）通过层间电介质到有源晶体管的源极结的第二开口; 以及用导电材料填充第一开口和第二开口以形成用于将沟槽电容器电连接到有源晶体管的漏极结的带，并且还形成用于将源极结连接到集成的上覆层 电路。

公开(公告)号：US07790530B2

公开(公告)日：2010-09-07

申请号：US12254960

申请日：2008-10-21

申请人： Jack A. Mandelman ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Geng Wang

发明人： Jack A. Mandelman ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Geng Wang

IPC分类号： H01L21/00

CPC分类号： H01L27/108 ,  H01L27/10829 ,  H01L27/10867 ,  H01L27/1203

摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.

摘要翻译： 使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。 具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。 各种增益单元布局在本领域中是已知的。 本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。 通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。