公开(公告)号：US20190027586A1

公开(公告)日：2019-01-24

申请号：US15654165

申请日：2017-07-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Haigou Huang

IPC: H01L29/66 ,  H01L29/78

Abstract: Structures for a vertical-transport field-effect transistor and methods for forming a structure for a vertical-transport field-effect transistor. A semiconductor fin is formed on a source/drain region. A gate stack is deposited that coats the semiconductor fin and a contact landing area of the source/drain region adjacent to the semiconductor fin. The gate stack is patterned to remove the gate stack from the contact landing area and to form a gate electrode having a section adjacent to the contact landing area. The section of the gate electrode is laterally recessed to form a cavity, and a dielectric spacer is formed in the cavity.

公开(公告)号：US10177037B2

公开(公告)日：2019-01-08

申请号：US15496429

申请日：2017-04-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Josef Watts

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/311 ,  H01L21/28 ,  H01L27/092 ,  H01L25/07 ,  H01L27/108

Abstract: A method includes providing a semiconductor structure having a substrate and a plurality of fins extending upwards from the substrate. A CT pillar layer is disposed over the semiconductor structure. A CT mask is lithographically patterned over the CT pillar layer. The CT mask is anisotropically etched to remove exposed portions of the CT pillar layer and to form a CT pillar between the fins. A dummy gate structure is disposed across the CT pillar. The dummy gate structure is replaced with first and second metal gate structures that are electrically isolated from each other by the CT pillar.

公开(公告)号：US10170482B2

公开(公告)日：2019-01-01

申请号：US15055571

申请日：2016-02-27

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Balasubramanian Pranatharthiharan ,  Hui Zang

IPC: H01L29/78 ,  H01L27/11 ,  H01L29/06 ,  H01L27/088 ,  H01L29/66 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/76 ,  H01L21/762 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/033 ,  H01L21/308 ,  H01L21/265

Abstract: A method for preventing epitaxial growth in a semiconductor device is described. The method includes cutting the fins of FinFET structure to form a set of exposed fin ends. A set of sidewall spacers are formed on the set of exposed fin ends, forming a set of spacer covered fin ends. The set of sidewall spacers prevent epitaxial growth at the set of spacer covered fin ends. A semiconductor device includes a set of fin structures having a set of fin ends. A set of inhibitory layers are disposed at the set of fin ends to inhibit excessive epitaxial growth at the fin ends.

公开(公告)号：US10170377B1

公开(公告)日：2019-01-01

申请号：US15709704

申请日：2017-09-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-Hwa Chi

IPC: H01L21/8239 ,  H01L27/11 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

Abstract: A method includes forming a device above an active region defined in a semiconducting substrate. The device includes a plurality of gate structures, a spacer formed adjacent each of the plurality of gate structures, and conductive source/drain contact structures positioned adjacent each of the plurality of gate structures and separated from the associated gate structure by the spacer. A first portion of the conductive source/drain contact structures of a subset of the plurality of gate structures is recessed at a first axial position along a selected gate structure of the plurality of gate structures to define a cavity. A selected source/drain contact structure is not recessed. A first dielectric layer is formed in the cavity. A conductive line contacting the selected source/drain contact structure in the first axial position is formed.

公开(公告)号：US10164041B1

公开(公告)日：2018-12-25

申请号：US15790216

申请日：2017-10-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Andreas Knorr ,  Julien Frougier ,  Hui Zang ,  Min-hwa Chi

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/49 ,  H01L29/786 ,  H01L27/088

Abstract: A method of forming a GAA FinFET, including: forming a fin on a substrate, the substrate having a STI layer formed thereon and around a portion of a FIN-bottom portion of the fin, the fin having a dummy gate formed thereover, the dummy gate having a gate sidewall spacer on sidewalls thereof; forming a FIN-void and an under-FIN cavity in the STI layer; forming first spacers by filling the under-FIN cavity and FIN-void with a first fill; removing the dummy gate, thereby exposing both FIN-bottom and FIN-top portions of the fin underneath the gate; creating an open area underneath the exposed FIN-top by removing the exposed FIN-bottom; and forming a second spacer by filling the open area with a second fill; wherein a distance separates a top-most surface of the second spacer from a bottom-most surface of the FIN-top portion. A GAA FinFET formed by the method is also disclosed.

公开(公告)号：US10163635B1

公开(公告)日：2018-12-25

申请号：US15797794

申请日：2017-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Hui Zang ,  Hsien-Ching Lo ,  Jerome Ciavatti ,  Judson Robert Holt

IPC: H01L21/033 ,  H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L29/861 ,  H01L29/78 ,  H01L49/02

Abstract: A method for preventing epitaxial merge between adjacent devices of a semiconductor is provided. Embodiments include forming a protection layer over a spacer formed over a first and second plurality of fins deposited within a substrate; pinching off a portion of the protection layer formed within a space between each of the plurality of fins; forming a planarization layer over the protection layer and the spacer; and etching a portion of the spacer to form inner sidewalls between each of the plurality of fins, outer sidewalls of a height greater than the height of the inner sidewalls for preventing the growth of the epitaxial layer beyond the outer sidewalls, or a combination thereof.

公开(公告)号：US20180366553A1

公开(公告)日：2018-12-20

申请号：US15624332

申请日：2017-06-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Bala Haran ,  Xuan Tran ,  Suryanarayana Kalaga

IPC: H01L29/49 ,  H01L23/535 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/768

Abstract: A method that includes forming an isolation material adjacent a fin, forming a sidewall spacer around a portion of the fin and above the isolation material and forming first and second conductive source/drain contact structures adjacent the sidewall spacer, wherein each of the first and second conductive source/drain contact structures has a side surface positioned proximate the sidewall spacer. In this example, the method further includes, after forming the source/drain contact structures, removing at least a portion of the sidewall spacer and forming a gate cap that is positioned above a final gate structure for the device, wherein the gate cap contacts the source/drain contact structures, and wherein an air gap is formed at least on opposite sides of the final gate structure above an active region of the device.

公开(公告)号：US10115807B2

公开(公告)日：2018-10-30

申请号：US15343821

申请日：2016-11-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Min-Hwa Chi ,  Jinping Liu

IPC: H01L21/30 ,  H01L29/66 ,  H01L29/08 ,  H01L21/306 ,  H01L21/02 ,  H01L29/78

Abstract: At least one method, apparatus and system disclosed herein fin field effect transistor (finFET) comprising a tall fin having a plurality of epitaxial regions. A first fin of a transistor is formed. The first fin comprising a first portion comprising silicon, a second portion comprising silicon germanium and a third portion comprising silicon. A gate structure above the third portion is formed. An etching process is performed for removing the silicon germanium of the second portion that is not below the gate structure. A first epitaxy region is formed above the first portion. A second epitaxy region is formed vertically aligned with the first epitaxy region and above the silicon germanium of the second portion that is below the gate structure.

公开(公告)号：US10109714B2

公开(公告)日：2018-10-23

申请号：US15694109

申请日：2017-09-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Tek Po Rinus Lee

IPC: H01L21/82 ,  H01L29/417 ,  H01L29/66 ,  H01L21/285 ,  H01L29/10 ,  H01L21/311 ,  H01L29/78

Abstract: Structures including a vertical field-effect transistor and fabrication methods for a structure including a vertical field-effect transistor. A vertical field-effect transistor includes a source/drain region located in a section of a semiconductor layer, a first semiconductor fin projecting from the source/drain region, a second semiconductor fin projecting from the source/drain region, and a gate electrode on the section of the semiconductor layer and coupled with the first semiconductor fin and with the second semiconductor fin. The structure further includes a contact located in a trench defined in the section of the semiconductor layer between the first semiconductor fin and the second semiconductor fin. The contact is coupled with the source/drain region of the vertical field-effect transistor.

公开(公告)号：US10109637B1

公开(公告)日：2018-10-23

申请号：US15856205

申请日：2017-12-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Randy W. Mann ,  Bipul C. Paul

IPC: H01L27/11 ,  H01L23/528 ,  H01L23/522 ,  H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45

Abstract: The disclosure provides integrated circuit (IC) structure including: a substrate; a shallow trench isolation (STI) positioned between the first and second regions of the substrate; a first transistor with a channel region is positioned on the first region of the substrate, and spacer positioned on the first region of the substrate and the STI; and a gate metal positioned on the spacer. The gate metal includes a gate contact region positioned over the first source/drain region of the substrate, and surrounding the channel region. Across-couple region extends laterally from the gate contact region to the source/drain region of a second transistor formed on the second region of the substrate.