公开(公告)号：US07045431B2

公开(公告)日：2006-05-16

申请号：US10738958

申请日：2003-12-17

申请人： Antonio L. P. Rotondaro ,  Douglas E. Mercer ,  Luigi Colombo ,  Mark Robert Visokay ,  Haowen Bu ,  Malcolm John Bevan

发明人： Antonio L. P. Rotondaro ,  Douglas E. Mercer ,  Luigi Colombo ,  Mark Robert Visokay ,  Haowen Bu ,  Malcolm John Bevan

IPC分类号： H01L21/336

CPC分类号： H01L21/28176 ,  H01L21/28194 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/6659

摘要： Methods are disclosed that fabricating semiconductor devices with high-k dielectric layers. The invention removes portions of deposited high-k dielectric layers not below gates and covers exposed portions (e.g., sidewalls) of high-k dielectric layers during fabrication with an encapsulation layer, which mitigates defects in the high-k dielectric layers and contamination of process tools. The encapsulation layer can also be employed as an etch stop layer and, at least partially, in comprising sidewall spacers. As a result, a semiconductor device can be fabricated with a substantially uniform equivalent oxide thickness.

摘要翻译： 公开了制造具有高k电介质层的半导体器件的方法。 本发明除了不在门下方的沉积的高k电介质层的部分，并且在用封装层制造期间覆盖高k电介质层的暴露部分（例如，侧壁），这减轻了高k电介质层中的缺陷和工艺污染 工具 封装层也可以用作蚀刻停止层，并且至少部分地包括侧壁间隔物。 结果，可以制造具有基本均匀的等效氧化物厚度的半导体器件。

公开(公告)号：US20050224874A1

公开(公告)日：2005-10-13

申请号：US11148805

申请日：2005-06-09

申请人： Srinivasan Chakravarthi ,  Pr Chrdambaram ,  Robert Bowen ,  Haowen Bu

发明人： Srinivasan Chakravarthi ,  Pr Chrdambaram ,  Robert Bowen ,  Haowen Bu

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/425 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/6653 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/91

摘要： A method of forming a retrograde well in a transistor is provided. A transistor structure having a substrate, a gate, and a gate oxide layer between the substrate and the gate is formed. The substrate includes a channel region located generally below the gate. A first dopant is implanted into the channel region. A second dopant is implanted into the substrate to form a doped source region and a doped drain region. A third dopant is implanted into the gate oxide layer. A source/drain anneal is performed to form a source and a drain in the doped source region and the doped drain region, respectively. The source/drain anneal causes a portion of the first dopant in the channel region to be attracted by the third dopant into the gate oxide layer.

公开(公告)号：US20050215037A1

公开(公告)日：2005-09-29

申请号：US10810759

申请日：2004-03-26

申请人： Jiong-Ping Lu ,  Haowen Bu ,  Shaofeng Yu ,  Ping Jiang

发明人： Jiong-Ping Lu ,  Haowen Bu ,  Shaofeng Yu ,  Ping Jiang

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/44 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/66507 ,  H01L21/28097 ,  H01L29/4975 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing the semiconductor device (100), among other possible steps, includes forming a polysilicon gate electrode over a substrate (110) and forming source/drain regions (170) in the substrate (110) proximate the polysilicon gate electrode. The method further includes forming a blocking layer (180) over the source/drain regions (170), the blocking layer (180) comprising a metal silicide, and siliciding the polysilicon gate electrode to form a silicided gate electrode (150).

摘要翻译： 本发明提供一种制造半导体器件的方法及其制造方法，该集成电路包括该半导体器件。 除了其他可能的步骤之外，用于制造半导体器件（100）的方法包括在衬底（110）上形成多晶硅栅电极，并在靠近多晶硅栅电极的衬底（110）中形成源/漏区（170）。 该方法还包括在源极/漏极区域（170）上形成阻挡层（180），阻挡层（180）包括金属硅化物，并硅化多晶硅栅电极以形成硅化物栅电极（150）。

公开(公告)号：US20050208776A1

公开(公告)日：2005-09-22

申请号：US11083912

申请日：2005-03-18

申请人： Anand Krishnan ,  Srinivasan Chakravarthi ,  Haowen Bu

发明人： Anand Krishnan ,  Srinivasan Chakravarthi ,  Haowen Bu

IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L21/318 ,  H01L21/469 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78

CPC分类号： H01L29/7842 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/02274 ,  H01L21/28211 ,  H01L21/31662 ,  H01L21/3185 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/7833

摘要： The present invention provides, in one aspect, a method of fabricating a gate oxide layer on a microelectronics substrate. This embodiment comprises forming a stress inducing pattern on a backside of a microelectronics wafer and growing a gate oxide layer on a front side of the microelectronics wafer in the presence of a tensile stress caused by the stress inducing pattern.

摘要翻译： 本发明在一个方面提供了一种在微电子衬底上制造栅氧化层的方法。 该实施例包括在微电子晶片的背面上形成应力诱导图案，并且在由应力诱导图案引起的拉伸应力的存在下，在微电子晶片的正面上生长栅极氧化物层。

公开(公告)号：US20050130442A1

公开(公告)日：2005-06-16

申请号：US10734708

申请日：2003-12-11

申请人： Mark Visokay ,  Luigi Colombo ,  James Chambers ,  Antonio Rotondaro ,  Haowen Bu

发明人： Mark Visokay ,  Luigi Colombo ,  James Chambers ,  Antonio Rotondaro ,  Haowen Bu

IPC分类号： H01L21/28 ,  H01L21/314 ,  H01L21/316 ,  H01L29/51 ,  H01L21/3205 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/28185 ,  H01L21/02148 ,  H01L21/02271 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/28202 ,  H01L21/3144 ,  H01L21/3162 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31691 ,  H01L29/517 ,  H01L29/518

摘要： Methods are disclosed for treating deposited gate dielectric materials, in which the deposited dielectric is subjected to one or more non-oxidizing anneals to densify the material, one or more oxidizing anneals to mitigate material defects, and to a nitridation process to introduce nitrogen into the gate dielectric. The annealing may be performed before and/or after the nitridation to mitigate deposition and/or nitridation defects and to densify the material while mitigating formation of unwanted low dielectric constant oxides at the interface between the gate dielectric and the semiconductor substrate.

摘要翻译： 公开了用于处理沉积的栅极电介质材料的方法，其中沉积的电介质经受一个或多个非氧化退火以致密化材料，一个或多个氧化退火以减轻材料缺陷，以及氮化过程以将氮引入 栅电介质。 可以在氮化之前和/或之后进行退火以减轻沉积和/或氮化缺陷并致密材料，同时减轻在栅极电介质和半导体衬底之间的界面处形成不想要的低介电常数氧化物。