公开(公告)号：US20220300160A1

公开(公告)日：2022-09-22

申请号：US17833645

申请日：2022-06-06

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Jianmin Huang ,  Ashutosh Malshe

IPC: G06F3/06

Abstract: An apparatus can include a media management threshold component. The media management threshold component can determine a first threshold quantity of blocks for a first memory mode in the memory device. The media management threshold component can determine a second threshold quantity of blocks for a second memory mode in the memory device. The media management threshold component can determine a logical saturation of the memory device. The media management threshold component can cause performance of a media management operation based on the determined first threshold quantity, the determined second threshold quantity, and a percentage of the determined logical saturation to a total logical saturation of the memory device.

公开(公告)号：US11437108B1

公开(公告)日：2022-09-06

申请号：US17230786

申请日：2021-04-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kishore Kumar Muchherla ,  Karl Schuh ,  Mustafa N Kaynak ,  Xiangang Luo ,  Shane Nowell ,  Devin Batutis ,  Sivagnanam Parthasarathy ,  Sampath Ratnam ,  Jiangang Wu ,  Peter Feeley

IPC: G11C16/34 ,  G11C16/30 ,  G11C16/10 ,  G11C7/04 ,  G11C16/32 ,  G11C16/26

Abstract: A difference between a current temperature and a prior temperature of a memory device is determined. In response to a determination that the difference between the current temperature and the prior temperature of the memory device satisfies a temperature criterion, an amount of voltage shift is measured for a set of memory cells of a block family associated with a first voltage bin of a set of voltage bins at the memory device. The first voltage bin is associated with a first voltage offset. An adjusted amount of voltage shift is determined for the set of memory cells based on the determined amount of voltage shift and a temporary voltage shift offset associated with the difference between the current temperature and the prior temperature for the memory device. In response to a determination that the adjusted amount of voltage shift satisfies a voltage shift criterion, the block family is associated with a second voltage bin of the set of voltage bins. The second voltage bin is associated with a second voltage offset.

公开(公告)号：US11360677B2

公开(公告)日：2022-06-14

申请号：US16948305

申请日：2020-09-11

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Karl D. Schuh ,  Jiangang Wu ,  Mustafa N. Kaynak ,  Devin M. Batutis ,  Xiangang Luo

IPC: G06F3/06

Abstract: A system includes a memory device having multiple of dice and a processing device operatively coupled to the memory device. The processing device performs operations including receiving memory operations to program sets of pages of data across at least a subset of the plurality of dice and identifying a plurality of the sets of pages experiencing a variation in a data state metric satisfying a threshold criterion. The operations further include partitioning, into a set of partitions, a set of pages of the plurality of the sets of pages, programming the set of partitions to the plurality of dice, and storing, in a metadata table, at least one bit to indicate that the first set of pages is partitioned.

公开(公告)号：US11307951B2

公开(公告)日：2022-04-19

申请号：US16560560

申请日：2019-09-04

Applicant: Micron Technology, Inc.

Inventor： Jianmin Huang ,  Xiangang Luo ,  Kulachet Tanpairoj

IPC: G06F11/00 ,  G06F11/30 ,  G11C29/02 ,  G06F12/14 ,  G11C16/14 ,  G06F11/07 ,  G06F11/34

Abstract: A memory device comprises a memory control unit including a processor configured to control operation of the memory array according to a first memory management protocol for memory access operations, the first memory management protocol including boundary conditions for multiple operating conditions comprising program/erase (P/E) cycles, error management operations, drive writes per day (DWPD), and power consumption; monitor operating conditions of the memory array for the P/E cycles, error management operations, DWPD, and power consumption; determine when a boundary condition for one of the multiple operating conditions is met; and in response to determining that a first boundary condition for a first monitored operating condition is met, change one or more operating conditions of the first memory management protocol to establish a second memory management protocol for the memory access operations, the second memory management protocol including a change boundary condition of a second monitored operating condition.

公开(公告)号：US20220066638A1

公开(公告)日：2022-03-03

申请号：US17002070

申请日：2020-08-25

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Jianmin Huang ,  Ashutosh Malshe

IPC: G06F3/06

Abstract: An apparatus can include a media management threshold component. The media management threshold component can determine a first threshold quantity of blocks for a first memory mode in the memory device. The media management threshold component can determine a second threshold quantity of blocks for a second memory mode in the memory device. The media management threshold component can determine a logical saturation of the memory device. The media management threshold component can cause performance of a media management operation based on the determined first threshold quantity, the determined second threshold quantity, and a percentage of the determined logical saturation to a total logical saturation of the memory device.

公开(公告)号：US11216349B2

公开(公告)日：2022-01-04

申请号：US16159132

申请日：2018-10-12

Applicant: Micron Technology, Inc.

Inventor： Harish Reddy Singidi ,  Vamsi Pavan Rayaprolu ,  Kishore Kumar Muchherla ,  Jianmin Huang ,  Xiangang Luo ,  Ashutosh Malshe

IPC: G06F11/20 ,  G06F3/06 ,  G06F11/10

Abstract: A variety of applications can include apparatus and/or methods to preemptively detect detect one memory blocks in a memory device and handle these memory blocks before they fail and trigger a data loss event. Metrics based on memory operations can be used to facilitate the examination of the memory blocks. One or more metrics associated with a memory operation on a block of memory can be tracked and a Z-score for each metric can be generated. In response to a comparison of a Z-score for a metric to a Z-score threshold for the metric, operations can be performed to control possible retirement of the memory block beginning with the comparison. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20210350871A1

公开(公告)日：2021-11-11

申请号：US17382926

申请日：2021-07-22

Applicant: Micron Technology, Inc.

Inventor： Jianmin Huang ,  Deping He ,  Xiangang Luo ,  Harish Reddy Singidi ,  Kulachet Tanpairoj ,  Xu Zhang ,  Ting Luo

IPC: G11C29/42 ,  G11C29/14 ,  G11C29/20 ,  G11C29/44 ,  G11C29/00

Abstract: Disclosed in some examples are NAND devices, firmware, systems, methods, and devices that apply smart algorithms to process ECC errors by taking advantage of excess overprovisioning. In some examples, when the amount of overprovisioned blocks are above a predetermined threshold, a first ECC block error handling mode may be implemented and when the overprovisioned blocks are equal or less than the predetermined threshold, a second mode of ECC block error handling may be utilized.

公开(公告)号：US10977115B2

公开(公告)日：2021-04-13

申请号：US16159027

申请日：2018-10-12

Applicant: Micron Technology, Inc.

Inventor： Harish Reddy Singidi ,  Xiangang Luo ,  Jianmin Huang ,  Kishore Kumar Muchherla ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Sampath Ratnam

IPC: G06F11/10 ,  G11C7/10 ,  G11C11/419 ,  G06F12/02

Abstract: Disclosed in some examples are techniques for handling parity data of a non-volatile memory device with limited cache memory. In certain examples, user data can be programmed into the non-volatile memory of the non-volatile memory device in data stripes, and parity information can be calculated for each individual data stripe within a limited capacity cache of the non-volatile memory device. The individual parity information can be swapped between a swap block of the non-volatile memory and the limited capacity cache as additional data stripes are programmed.

公开(公告)号：US20210098030A1

公开(公告)日：2021-04-01

申请号：US17122531

申请日：2020-12-15

Applicant: Micron Technology, Inc

Inventor： Xiangang Luo ,  Jianmin Huang ,  Patroclo Fumagalli ,  Scott Anthony Stoller ,  Alessandro Magnavacca ,  Andrea Pozzato

IPC: G11C5/14 ,  G06F11/07 ,  G11C29/38 ,  G11C11/4099

Abstract: Systems and methods are disclosed, including determining whether to write dummy data to a first physical page of memory cells of a storage system, such as in response to a detected asynchronous power loss (APL) at the storage system, using a determined number of zeros in the first physical page.

公开(公告)号：US20210042181A1

公开(公告)日：2021-02-11

申请号：US16533328

申请日：2019-08-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vamsi Pavan Rayaprolu ,  Harish R. Singidi ,  Kishore Kumar Muchherla ,  Ashutosh Malshe ,  Xiangang Luo

IPC: G06F11/07

Abstract: A memory access operation can be determined to have failed. A determination can be made as to whether a performance of a first error control operation has remedied the failure of the memory access operation. In response to determining that the first error control operation has remedied the failure of the memory access operation, an order of a performance of one or more prioritized error control operations of the plurality of prioritized error control operations can be changed for a subsequent memory access operation that has failed based on the first error control operation that has remedied the failure.