公开(公告)号：US06809961B2

公开(公告)日：2004-10-26

申请号：US10331116

申请日：2002-12-27

申请人： Rino Micheloni ,  Sabina Mognoni ,  Ilaria Motta ,  Andrea Sacco

发明人： Rino Micheloni ,  Sabina Mognoni ,  Ilaria Motta ,  Andrea Sacco

IPC分类号： G11C1604

CPC分类号： G11C16/30

摘要： A method and program-load circuit is for regulating the voltages at the drain and body terminals of a non-volatile memory cell being programmed. These voltages are applied from a program-load circuit connected in a conduction pattern to transfer a predetermined voltage value to at least one terminal of the memory cell. The method includes a step of regulating the voltage value locally, within the program-load circuit, to overcome the effect of a parasitic resistor present in the conduction pattern.

摘要翻译： 一种方法和程序加载电路用于调节正被编程的非易失性存储单元的漏极和体端子处的电压。 这些电压从连接在导通图案中的编程负载电路施加，以将预定的电压值传送到存储单元的至少一个端子。 该方法包括在编程负载电路内局部调节电压值以克服存在于导电图案中的寄生电阻的影响的步骤。

公开(公告)号：US06724658B2

公开(公告)日：2004-04-20

申请号：US10133231

申请日：2002-04-26

申请人： Rino Micheloni ,  Giovanni Campardo

发明人： Rino Micheloni ,  Giovanni Campardo

IPC分类号： G11C1600

CPC分类号： G11C11/5621 ,  G11C5/147 ,  G11C7/067 ,  G11C11/56 ,  G11C11/5642 ,  G11C11/565 ,  G11C16/26 ,  G11C2211/5634

摘要： The circuit for generating reference voltages for reading a multilevel memory cell includes the following: a first memory cell and a second memory cell respectively having a first reference programming level and a second reference programming level; a first reference circuit and a second reference circuit respectively connected to said first and said second memory cells and having respective output terminals which respectively supply a first reference voltage and a second reference voltage; and a voltage divider having a first connection node and a second connection node respectively connected to the output terminals of the first reference circuit and of the second reference circuit to receive, respectively, the first reference voltage and the second reference voltage, and a plurality of intermediate nodes supplying respective third reference voltages at equal distances apart.

摘要翻译： 用于产生用于读取多电平存储器单元的参考电压的电路包括：分别具有第一参考编程电平和第二参考编程电平的第一存储单元和第二存储单元; 分别连接到所述第一和所述第二存储单元的第一参考电路和第二参考电路，并具有分别提供第一参考电压和第二参考电压的相应输出端; 以及分压器，具有分别连接到第一参考电路和第二参考电路的输出端的第一连接节点和第二连接节点，以分别接收第一参考电压和第二参考电压，以及多个 中间节点以相等的距离提供相应的第三参考电压。

公开(公告)号：US06642776B1

公开(公告)日：2003-11-04

申请号：US09541577

申请日：2000-04-03

申请人： Rino Micheloni ,  Luca Crippa

发明人： Rino Micheloni ,  Luca Crippa

IPC分类号： G05F110

CPC分类号： G05F3/30

摘要： Bandgap voltage reference circuit with an output voltage that remains stable in the range of a temperature of utilization. The circuit includes a first circuit block, a second circuit block, and a control circuit connected with said circuit blocks, said first circuit block including a bandgap circuit with a low power consumption, said second circuit block including a bandgap circuit with a short start up time, said control circuit suitable to control said two circuit blocks in a such way that said output voltage of said bandgap voltage reference circuit is supplied by said second circuit block at the starting of said first circuit block for a period of time and said output voltage is supplied by said first circuit block for the period of time subsequent to said period of time and that lasts until the turning off of the circuit, said second circuit block being turned off after said period of time.

摘要翻译： 带隙电压参考电路，输出电压在使用温度范围内保持稳定。 电路包括第一电路块，第二电路块和与所述电路块连接的控制电路，所述第一电路块包括具有低功耗的带隙电路，所述第二电路块包括具有短启动的带隙电路 所述控制电路适于以这样的方式控制所述两个电路块，使得所述带隙电压参考电路的所述输出电压在所述第一电路块的启动期间由所述第二电路块提供一段时间，并且所述输出电压 由所述第一电路块供给所述时间段之后的时间段，并持续到所述电路的断开，所述第二电路块在所述时间段之后被关断。

公开(公告)号：US06603681B2

公开(公告)日：2003-08-05

申请号：US10002599

申请日：2001-10-31

申请人： Rino Micheloni ,  Andrea Sacco

发明人： Rino Micheloni ,  Andrea Sacco

IPC分类号： G11C1604

CPC分类号： G11C16/24 ,  G11C16/10

摘要： A pulse programming method for a non-volatile memory device includes: addressing memory cells to be programmed within the device by selecting corresponding hierarchic decoder transistors; biasing the gate terminals of the memory cells; and programming the memory cells by applying a voltage pulse, regulated by a bias circuit, to the drain terminals of the memory cells. Advantageously, the programming method further comprises a step of precharging an internal node of the bias circuit before starting the programming step, the internal node being connected to a parasitic capacitance of the memory device.

公开(公告)号：US06532171B2

公开(公告)日：2003-03-11

申请号：US09919789

申请日：2001-07-31

申请人： Roberto Gastaldi ,  Paolo Cappelletti ,  Giulio Casagrande ,  Giovanni Campardo ,  Rino Micheloni

发明人： Roberto Gastaldi ,  Paolo Cappelletti ,  Giulio Casagrande ,  Giovanni Campardo ,  Rino Micheloni

IPC分类号： G11C1616

CPC分类号： G11C16/3431 ,  G11C16/16 ,  G11C16/34

摘要： A semiconductor memory such as a flash memory, which comprises at least one two-dimensional array of memory cells with a plurality of rows and columns of memory cells grouped in a plurality of packets. The memory cells belonging to the columns of each packet are formed in a respective semiconductor region with a first type of conductivity, this region being distinct from the semiconductor regions with the first type of conductivity in which the memory cells belonging to the columns of the remaining packets are formed. The semiconductor regions with the first type of conductivity divide the set of memory cells belonging to each row into a plurality of subsets of memory cells that constitute elemental memory units which can be modified individually. Thus memory units of very small dimensions can be erased individually, without excessive overhead in terms of area.

摘要翻译： 诸如闪速存储器的半导体存储器，其包括具有分组在多个分组中的多个存储单元的行和列的存储器单元的至少一个二维阵列。 属于每个分组的列的存储单元形成在具有第一类型导电性的相应半导体区域中，该区域与具有第一类型导电性的半导体区域不同，其中存储单元属于剩余的列 形成包。 具有第一类型导电性的半导体区域将属于每一行的存储单元集合分成多个存储单元子集，这些存储单元子集构成可单独修改的元素存储单元。 因此，可以单独擦除非常小尺寸的存储单元，而在面积方面没有过多的开销。

公开(公告)号：US06356481B1

公开(公告)日：2002-03-12

申请号：US09595054

申请日：2000-06-16

申请人： Rino Micheloni ,  Giovanni Campardo ,  Atsushi Ohba ,  Marcello Carrera

发明人： Rino Micheloni ,  Giovanni Campardo ,  Atsushi Ohba ,  Marcello Carrera

IPC分类号： G11C1606

CPC分类号： G11C11/5621 ,  G11C8/08 ,  G11C8/14 ,  G11C16/08 ,  G11C16/12 ,  G11C16/30

摘要： The row decoder includes, for each word line of the memory, a respective biasing circuit receiving at the input a row selection signal switching, in preset operating conditions, between a supply voltage and a ground voltage and supplying at the output a biasing signal for the respective word line switching between a first operating voltage, in turn switching at least between the supply voltage and a programming voltage higher than the supply voltage, and a second operating voltage, in turn switching at least between the ground voltage and an erase voltage lower than the ground voltage. Each biasing circuit includes a level translator circuit receiving at the input the row selection signal and supplying as output a control signal switching between the first and the second operating voltages and an output driver circuit receiving as input the control signal and supplying at the output the biasing signal.

摘要翻译： 行解码器包括对于存储器的每个字线，相应的偏置电路在输入端接收行选择信号，在预设工作条件下，在电源电压和接地电压之间切换，并在输出端提供偏置信号， 相应的字线在第一工作电压之间切换，进而至少在电源电压和高于电源电压的编程电压之间切换，以及第二工作电压，进而至少在接地电压和擦除电压之间切换 接地电压。 每个偏置电路包括电平转换器电路，其在输入处接收行选择信号，并且作为输出提供在第一和第二操作电压之间切换的控制信号;以及输出驱动器电路，作为输入接收控制信号，并在输出端提供偏置 信号。

公开(公告)号：US06351413B1

公开(公告)日：2002-02-26

申请号：US09552945

申请日：2000-04-20

申请人： Rino Micheloni ,  Giovanni Campardo ,  Stefano Commodaro ,  Francesco Farina

发明人： Rino Micheloni ,  Giovanni Campardo ,  Stefano Commodaro ,  Francesco Farina

IPC分类号： G11C1604

CPC分类号： G11C16/08 ,  G11C5/025 ,  G11C7/18 ,  G11C8/10

摘要： The memory array comprises a plurality of cells, grouped together in sectors and arranged in sector rows and columns, and has both hierarchical row decoding and hierarchical column decoding. Global word lines are connected to at least two word lines in each sector, through local row decoders; global bit lines are connected to at least two local bit lines in each sector, through local column decoders. The global column decoder is arranged in the center of the memory array, and separates from each other an upper half and a lower half of the memory array. Sense amplifiers are also arranged in the middle of the array, thus saving space. This architecture also provides lesser stress of the cells, better reliability, and better production performance. In addition, each sector is completely disconnected from the remaining sectors, and only the faulty row or column of a single sector should be doubled.

摘要翻译： 存储器阵列包括多个单元，分组在扇区中并以扇区行和列排列，并且具有分级行解码和分层列解码。 全局字线通过局部行解码器连接到每个扇区中的至少两个字线; 全局位线通过本地列解码器连接到每个扇区中的至少两个局部位线。 全局列解码器被布置在存储器阵列的中心，并且彼此分离存储器阵列的上半部和下半部。 感应放大器也布置在阵列的中间，从而节省空间。 该架构还提供更小的电池应力，更好的可靠性和更好的生产性能。 此外，每个扇区与其余扇区完全断开连接，只有单个扇区的故障行或列应该加倍。

公开(公告)号：US06307778B1

公开(公告)日：2001-10-23

申请号：US09658236

申请日：2000-09-08

申请人： Rino Micheloni ,  Andrea Sacco ,  Sabina Mognoni

发明人： Rino Micheloni ,  Andrea Sacco ,  Sabina Mognoni

IPC分类号： G11C1606

CPC分类号： G11C29/50 ,  G01R31/3004 ,  G11C29/02

摘要： The non volatile memory device integrates, in one and the same chip, the array of memory cells, a voltage regulator which supplies a regulated operating voltage to a selected word line, and a short circuit detecting circuit. The short circuit detecting circuit detects the output voltage of the voltage regulator, which is correlated to the current for biasing the cells of the word line selected. Once settled to the steady state condition, the output current assumes one first value in the absence of short circuits, and one second value in the presence of a short circuit between the word line selected and one or more adjacent word lines. The short circuit detecting circuit compares the output current of the voltage regulator with a reference value and generates at output a short circuit digital signal which indicates the presence or otherwise of a short circuit.

摘要翻译： 非易失性存储器件在同一芯片中集成了存储单元阵列，向所选字线提供调节工作电压的电压调节器和短路检测电路。 短路检测电路检测电压调节器的输出电压，其与用于偏置所选字线的单元的电流相关。 一旦稳定到稳定状态，输出电流在没有短路的情况下呈现一个第一值，并且在所选择的字线和一个或多个相邻字线之间存在短路的情况下，存在一个第二值​​。 短路检测电路将电压调节器的输出电流与参考值进行比较，并在输出端产生指示短路的存在或短路的短路数字信号。

公开(公告)号：US06301152B1

公开(公告)日：2001-10-09

申请号：US09570332

申请日：2000-05-12

申请人： Giovanni Campardo ,  Alessandro Manstretta ,  Rino Micheloni

发明人： Giovanni Campardo ,  Alessandro Manstretta ,  Rino Micheloni

IPC分类号： G11C1606

CPC分类号： G11C29/846

摘要： A non-volatile memory device is organized with memory cells that are arranged by row and by column. The memory device includes a sector of matrix cells, row decoders and column decoders suitable to decode address signals and to activate respectively the rows or said columns, at least a sector of redundancy cells such that it is possible to substitute a row of the sector of matrix cells with a row of the sector of redundancy cells. The non-volatile memory device comprises a local column decoder for the matrix sector and a local column decoder for the redundancy sector. The local column decoders are controlled by external signals so that the row of the redundancy sector is activated simultaneously with the row of the matrix sector.

摘要翻译： 非易失性存储器件被组织成具有按行和列排列的存储器单元。 存储器件包括矩阵单元的扇区，行解码器和列解码器，其适于解码地址信号，并分别激活行或所述列，至少冗余单元的扇区，使得可以将行的一行替换为 具有冗余单元扇区行的矩阵单元。 非易失性存储器件包括用于矩阵扇区的本地列解码器和用于冗余扇区的本地列解码器。 本地列解码器由外部信号控制，使得冗余扇区的行与矩阵扇区的行同时激活。

公开(公告)号：US6111809A

公开(公告)日：2000-08-29

申请号：US324087

申请日：1999-06-01

申请人： Rino Micheloni ,  Giovanni Campardo

发明人： Rino Micheloni ,  Giovanni Campardo

IPC分类号： G11C8/10 ,  G11C8/00

CPC分类号： G11C8/10

摘要： A decoder comprises a first line placed at a first reference potential (V.sub.CC); a second line placed at a second reference potential switchable between the first reference potential and at least one programming potential higher than the first reference potential; a voltage elevator circuit connected to the second line, receiving a control signal and generating at an output a third reference potential switchable, on the basis of the control signal, between the first reference potential, the programming potential and a boosted potential which is between the first reference potential and the reference potential; a third line connected to the output of the voltage elevator circuit; an input circuit connected to the first line and receiving a predecoding signal, an output biasing circuit connected to said third line and generating a biasing signal for one line of the memory device; and switch circuit located between the input circuit and the biasing circuit, receiving a driving signal for selectively breaking the electrical connection between the input circuit and the biasing circuit on the basis of the driving signal.

摘要翻译： 解码器包括放置在第一参考电位（VCC）的第一线; 放置在可在第一参考电位和高于第一参考电位的至少一个编程电位之间切换的第二参考电位的第二行; 连接到第二线路的电压升降机电路，接收控制信号，并在输出端产生基于控制信号切换第三参考电位的第一参考电位，编程电位和在第二参考电位之间的升压电位 第一参考电位和参考电位; 连接到电压升降电路的输出的第三线; 连接到所述第一线并接收预解码信号的输入电路，连接到所述第三线并输出所述存储器件的一行的偏置信号的输出偏置电路; 以及位于输入电路和偏置电路之间的开关电路，基于驱动信号接收用于选择性地断开输入电路和偏置电路之间的电连接的驱动信号。