公开(公告)号：US09844065B2

公开(公告)日：2017-12-12

申请号：US14755827

申请日：2015-06-30

Applicant: QUALCOMM Incorporated

Inventor： Richard Dominic Wietfeldt

IPC: H04W52/00 ,  H04W72/08 ,  H04W8/00 ,  H04W40/24 ,  H04W48/16 ,  H04W88/06 ,  H04W88/10 ,  H04W88/18 ,  H04W72/04

CPC classification number: H04W72/085 ,  H04W8/005 ,  H04W40/244 ,  H04W48/08 ,  H04W48/16 ,  H04W72/046 ,  H04W72/082 ,  H04W88/06 ,  H04W88/10 ,  H04W88/184

Abstract: Systems and methods are disclosed for optimizing the reach of a message beacon device. The method may include identifying a plurality of transceivers associated with the message beacon device, analyzing each identified transceiver on the basis of a resource consumption associated with the identified transceiver, an interference of the identified transceiver with a different transceiver of the plurality of identified transceivers, a reach of the identified transceiver, or a combination thereof, selecting a transmission set from the plurality of identified transceivers based on the analysis of each identified transceiver, and transmitting a message beacon using each selected transceiver in the transmission set.

公开(公告)号：US20170329737A1

公开(公告)日：2017-11-16

申请号：US15151682

申请日：2016-05-11

Applicant: QUALCOMM Incorporated

Inventor： Nitinkumar Barot ,  Lalan Jee Mishra ,  Richard Dominic Wietfeldt

IPC: G06F13/42 ,  G06F13/362

CPC classification number: G06F13/4282 ,  G06F13/362 ,  G06F13/405

Abstract: Systems, methods, and apparatus for bridging between different types of serial interface are disclosed. A method performed by a bridge circuit includes synchronizing transmissions on a 4-wire serial interface with transmissions on a 2-wire serial interface when a stop bit is detected on data lines of at least one interface, receiving a first clear-to-send notification from a first wire of the 2-wire serial interface, asserting a request-to-send signal on a first flow-control line of the 4-wire serial interface, receiving data bits from a first data line of the 4-wire serial interface while the request-to-send signal is asserted, and transmitting the data bits on the first wire of the 2-wire serial interface after receiving the first clear-to-send notification.

公开(公告)号：US20170212850A1

公开(公告)日：2017-07-27

申请号：US15002558

申请日：2016-01-21

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt

IPC: G06F13/18 ,  G06F13/364 ,  G06F13/42 ,  H04L12/40

CPC classification number: G06F13/18 ,  G06F12/1425 ,  G06F13/364 ,  G06F13/385 ,  G06F13/4282 ,  H04L12/40143 ,  H04L12/40182 ,  H04L12/403

Abstract: Priority-based data communication over multiple communication buses is disclosed. In this regard, an electronic device is communicatively coupled to a first communication bus and a second communication bus. The electronic device is configured to detect communication signals communicated over the first communication bus and the second communication bus. If the communication signals are detected on both the first communication bus and the second communication bus, the electronic device is further configured to protect data received over the second communication bus from being overwritten by data received over the first communication bus. By configuring the electronic device to support multiple communication buses, it is possible to configure one of the multiple communication buses as a priority communication bus, thus allowing time-critical communications to be carried out over the priority communication bus in a timely manner without preempting ongoing communications on other communication buses.

公开(公告)号：US20170075852A1

公开(公告)日：2017-03-16

申请号：US15242368

申请日：2016-08-19

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Radu Pitigoi-Aron

IPC: G06F13/42 ,  G06F15/17 ,  G06F13/40 ,  G06F15/177

CPC classification number: G06F13/4282 ,  G06F13/385 ,  G06F13/4022 ,  G06F15/17 ,  G06F15/177

Abstract: In an aspect, an integrated circuit obtains a set of general purpose input/output (GPIO) signals for one or more peripheral devices, obtains a first virtual GPIO packet that includes the set of GPIO signals independent of a central processing unit, and transmits the first virtual GPIO packet to the one or more peripheral devices over an I3C bus independent of the central processing unit. The integrated circuit may further obtain a set of configuration signals for configuring one or more GPIO pins of the one or more peripheral devices, obtain a second virtual GPIO packet that includes the set of configuration signals independent of the central processing unit, and transmit the second virtual GPIO packet to the one or more peripheral devices over the I3C bus independent of the central processing unit.

Abstract translation: 一方面，集成电路获得用于一个或多个外围设备的一组通用输入/输出（GPIO）信号，获得独立于中央处理单元的包括一组GPIO信号的第一虚拟GPIO分组，并发送 第一个虚拟GPIO数据包通过独立于中央处理单元的I3C总线上的一个或多个外设。 集成电路还可以获得用于配置一个或多个外围设备的一个或多个GPIO引脚的一组配置信号，获得包括独立于中央处理单元的一组配置信号的第二虚拟GPIO分组，并且发送第二个 虚拟GPIO数据包到I3C总线上的一个或多个外设，独立于中央处理器。

公开(公告)号：US20170075843A1

公开(公告)日：2017-03-16

申请号：US14850104

申请日：2015-09-10

Applicant: QUALCOMM Incorporated

Inventor： Richard Dominic Wietfeldt ,  Maxime Leclercq ,  George Alan Wiley

IPC: G06F13/40

CPC classification number: G06F13/4027 ,  G06F13/385 ,  G06F13/4068 ,  H04L43/0817

Abstract: Unified systems and methods for interchip and intrachip node communication are disclosed. In one aspect, a single unified low-speed bus is provided that connects each of the chips within a computing device. The chips couple to the bus through a physical layer interface and associated gateway. The gateway includes memory that stores a status table summarizing statuses for every node in the interface fabric. As nodes experience state changes, the nodes provide updates to associated local gateways. The local gateways then message, using a scout message, remote gateways with information relating to the state changes. When a first node is preparing a signal to a second node, the first node checks the status table at the associated local gateway to determine a current status for the second node. Based on the status of the second node, the first node may send the message or take other appropriate action.

Abstract translation: 公开了用于芯片间和节点间通信的统一系统和方法。 在一个方面，提供了连接计算设备内的每个芯片的单个统一的低速总线。 芯片通过物理层接口和相关网关耦合到总线。 网关包括存储状态表的内存，其汇总接口结构中每个节点的状态。 当节点经历状态改变时，节点向相关联的本地网关提供更新。 然后，本地网关使用侦察器消息来发送具有与状态改变有关的信息的远程网关。 当第一节点准备到第二节点的信号时，第一节点检查相关联的本地网关处的状态表以确定第二节点的当前状态。 基于第二节点的状态，第一节点可以发送消息或采取其他适当的动作。

公开(公告)号：US20160246570A1

公开(公告)日：2016-08-25

申请号：US14631078

申请日：2015-02-25

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  George Alan Wiley

IPC: G06F5/16 ,  G06F5/06 ,  G06F1/12 ,  G06F13/40 ,  G06F13/16

CPC classification number: G06F5/16 ,  G06F1/12 ,  G06F5/065 ,  G06F13/1673 ,  G06F13/385 ,  G06F13/4022

Abstract: A line multiplexed UART interface is provided that multiplexes a UART transmit and CTS functions on a transmit pin and that multiplexes a UART receive and RTS functions on a receive pin. In this fashion, the conventional need for an additional RTS pin and an additional CTS pin is obviated such that the line multiplexed UART interface uses just the transmit pin and the receive pin.

Abstract translation: 提供了一种线路复用UART接口，可在发送引脚上复用UART发送和CTS功能，并在接收引脚上复用UART接收和RTS功能。 以这种方式，消除了额外的RTS引脚和附加CTS引脚的常规需求，使得线路复用UART接口仅使用发送引脚和接收引脚。

公开(公告)号：US20160234748A1

公开(公告)日：2016-08-11

申请号：US14616545

申请日：2015-02-06

Applicant: QUALCOMM Incorporated

Inventor： George Chrisikos ,  Richard Dominic Wietfeldt

IPC: H04W36/30 ,  H04L12/26 ,  H04W24/08 ,  H04W36/20

CPC classification number: H04W36/30 ,  G01S19/21 ,  H04B15/00 ,  H04L43/065 ,  H04W24/08 ,  H04W36/20 ,  H04W72/1215 ,  H04W88/06

Abstract: Various arrangements are presented for managing co-existence of a global navigation satellite system (GNSS) receiver with one or more transceivers. A coexistence manager may obtain one or more parameters associated with a first transceiver of the one or more transceivers operating in accordance with a first radio access technology (RAT) and corresponding to an operating event. The first transceiver may be capable of operating in accordance with one or more RATs. The coexistence manager may further determine that the one or more parameters impacts an operation of the GNSS receiver and exceeds a predefined threshold and instruct the first transceiver to perform at least one of selecting a second RAT, changing the one or more parameters or any combination thereof to transmit at least a first portion of a data corresponding to the operating event based on the determination that the one or more parameters impacts the operation of the GNSS receiver.

Abstract translation: 提出了各种安排，用于管理具有一个或多个收发器的全球导航卫星系统（GNSS）接收机的共存。 共存管理器可以获得与根据第一无线电接入技术（RAT）并且对应于操作事件操作的一个或多个收发器的第一收发器相关联的一个或多个参数。 第一收发器可以能够根据一个或多个RAT进行操作。 共存管理器还可以确定一个或多个参数影响GNSS接收机的操作并超过预定义的阈值，并指示第一收发器执行选择第二RAT，改变一个或多个参数或其任何组合中的至少一个 基于所述一个或多个参数影响GNSS接收机的操作的确定来发送对应于所述操作事件的数据的至少第一部分。

公开(公告)号：US20160179741A1

公开(公告)日：2016-06-23

申请号：US14578831

申请日：2014-12-22

Applicant: QUALCOMM Incorporated

Inventor： Richard Dominic Wietfeldt

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4221 ,  G06F13/4022 ,  G06F13/409 ,  G06F13/4282 ,  G06F13/4295 ,  G06F15/163 ,  H04B15/02 ,  H04L12/40169

Abstract: Dynamic lane management for interference mitigation is disclosed. In one aspect, an integrated circuit (IC) is provided that employs a control system configured to mitigate electromagnetic interference (EMI) caused by an aggressor communications bus. The control system is configured to receive information related to EMI conditions and adjust which lanes of the aggressor communications bus are employed for signal transmission. The IC includes an interface configured to couple to the aggressor communications bus. The interface is configured to transmit signals to and receive signals from the aggressor communications bus. The control system is configured to use the information related to the EMI conditions to assign signals to be transmitted via particular lanes of the aggressor communications bus to mitigate the EMI experienced by a victim receiver. The control system provides designers with an additional tool that may reduce the performance degradation of the victim receiver attributable to EMI.

Abstract translation: 公开了用于干扰减轻的动态车道管理。 在一个方面，提供了一种集成电路（IC），其采用被配置为减轻由侵略者通信总线引起的电磁干扰（EMI）的控制系统。 控制系统被配置为接收与EMI条件相关的信息，并且调整侵入者通信总线的哪些通道用于信号传输。 IC包括被配置为耦合到侵略者通信总线的接口。 该接口被配置为向侵入者通信总线发送信号并从其接收信号。 控制系统被配置为使用与EMI条件相关的信息来分配要通过侵略者通信总线的特定通道发送的信号，以减轻受害者接收机所经历的EMI。 控制系统为设计人员提供了一个额外的工具，可以降低受EMI接收机的性能下降。

公开(公告)号：US20160077995A1

公开(公告)日：2016-03-17

申请号：US14850809

申请日：2015-09-10

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  James Lionel Panian ,  Radu Pitigoi-Aron

IPC: G06F13/42 ,  G06F1/10

CPC classification number: G06F13/4221 ,  G06F1/10 ,  G06F13/385

Abstract: A virtual GPIO interface is provided that receives a transmit set of GPIO signals from a processor. The virtual GPIO interface transmits a portion of the transmit set of GPIO signals over GPIO pins in a conventional fashion. However, the virtual GPIO interface provides a remaining portion of the transmit set of GPIO signals to a finite state machine that serializes the GPIO signals in the remaining portion into frames of virtual GPIO signals. A modified UART interface transmits the frames over a UART transmit pin responsive to cycles of a UART oversampling clock.

Abstract translation: 提供了一个从处理器接收GPIO信号发送组件的虚拟GPIO接口。 虚拟GPIO接口以传统方式通过GPIO引脚传输GPIO信号发送组的一部分。 然而，虚拟GPIO接口将GPIO信号发送组的剩余部分提供给有限状态机，将剩余部分中的GPIO信号序列化为虚拟GPIO信号帧。 一个经过修改的UART接口可以响应UART过采样时钟的周期，通过UART发送引脚发送帧。

公开(公告)号：US20150023454A1

公开(公告)日：2015-01-22

申请号：US14336977

申请日：2014-07-21

Applicant: QUALCOMM Incorporated

Inventor： Chulkyu Lee ,  George Alan Wiley ,  Richard Dominic Wietfeldt

IPC: H04L7/00

CPC classification number: H04L7/033 ,  G06F13/4295 ,  H04B3/50 ,  H04L7/00 ,  H04L7/0037 ,  H04L7/0041

Abstract: Systems and methods for multi-phase signaling are described herein. In one embodiment, a method for receiving data comprises receiving a sequence of symbols from a plurality of conductors, and generating a clock signal by detecting transitions in the received sequence of symbols. The method also comprises delaying the received sequence of symbols, and capturing one or more symbols in the delayed sequence of symbols using the clock signal, wherein a previous symbol in the delayed sequence of symbols is captured using a clock pulse in the clock signal generated based on a detected transition to a current symbol in the received sequence of symbols.

Abstract translation: 本文描述了用于多相信令的系统和方法。 在一个实施例中，一种用于接收数据的方法包括从多个导体接收符号序列，以及通过检测所接收的符号序列中的转变来产生时钟信号。 该方法还包括延迟接收到的符号序列，并使用时钟信号捕获延迟符号序列中的一个或多个符号，其中使用基于时钟信号生成的时钟信号中的时钟脉冲来捕获延迟符号序列中的先前符号 在所接收的符号序列中检测到到当前符号的转换。