公开(公告)号：US20160188408A1

公开(公告)日：2016-06-30

申请号：US14587234

申请日：2014-12-31

Applicant: Texas Instruments Incorporated

Inventor： Timothy Anderson ,  Joseph Zbiciak ,  Abhijeet A. Chachad ,  Kai Chirca ,  Naveen Bhoria ,  David M. Thompson ,  Jonathan (Son) Hung Tran

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F3/0673 ,  G06F3/0619 ,  G06F3/064 ,  G06F11/1048

Abstract: This invention is data processing apparatus and method. Data is protecting from corruption using an error correction code by generating an error correction code corresponding to the data. In this invention the data and the corresponding error correction code are carried forward to another set of registers without regenerating the error correction code or using the error correction code for error detection or correction. Only later are error correction detection and correction actions taken. The differing data/error correction code registers may be in differing pipeline phases in the data processing apparatus. This invention forwards the error correction code with the data through the entire datapath that carries the data. This invention provides error protection to the whole datapath without requiring extensive hardware or additional time.

Abstract translation: 本发明是数据处理装置和方法。 通过产生对应于该数据的纠错码，使用纠错码来防止数据损坏。 在本发明中，将数据和相应的纠错码转发到另一组寄存器，而不用再生纠错码或使用纠错码进行错误检测或校正。 只有以后才采取纠错检测和纠正措施。 在数据处理装置中不同的数据/纠错码寄存器可能处于不同的流水线相位。 本发明通过携带数据的整个数据路径转发具有数据的纠错码。 本发明为整个数据路径提供错误保护，而不需要大量硬件或额外的时间。

公开(公告)号：US09244837B2

公开(公告)日：2016-01-26

申请号：US13649269

申请日：2012-10-11

Applicant: Texas Instruments Incorporated

Inventor： Naveen Bhoria ,  Raguram Damodaran ,  Abhijeet Ashok Chachad

IPC: G06F12/00 ,  G06F12/08 ,  G06F12/12 ,  G06F13/28

CPC classification number: G06F12/0808 ,  G06F12/08 ,  G06F12/0811 ,  G06F12/0891 ,  G06F12/122 ,  G06F13/28 ,  G06F2212/1021 ,  G06F2212/62 ,  Y02D10/13

Abstract: A method to eliminate the delay of a block invalidate operation in a multi CPU environment by overlapping the block invalidate operation with normal CPU accesses, thus making the delay transparent. A range check is performed on each CPU access while a block invalidate operation is in progress, and an access that maps to within the address range of the block invalidate operation is treated as a cache miss to ensure that the requesting CPU will receive valid data.

Abstract translation: 通过将块无效操作与正常CPU访问重叠来消除多CPU环境中的块无效操作的延迟的方法，从而使得延迟变得透明。 在块无效操作正在进行时，对每个CPU访问执行范围检查，并将映射到块无效操作的地址范围内的访问视为高速缓存未命中，以确保请求的CPU将接收有效数据。

公开(公告)号：US08930783B2

公开(公告)日：2015-01-06

申请号：US13709188

申请日：2012-12-10

Applicant: Texas Instruments Incorporated

Inventor： Raguram Damodaran ,  Naveen Bhoria ,  Aman Kokrady

IPC: G01R31/28 ,  G11C29/12 ,  G01R31/3185 ,  G11C29/36

CPC classification number: G11C29/12 ,  G01R31/318519 ,  G01R31/318555 ,  G11C17/00 ,  G11C29/16 ,  G11C29/36 ,  G11C2029/0401

Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where a plurality of memories requiring different testing conditions are incorporated in an SOC. The pBIST Read Only Memory storing the test setup data is organized to eliminate multiple instances of test setup data for similar embedded memories.

Abstract translation: 用于测试嵌入式存储器的可编程内建自测（pBIST）系统，其中需要不同测试条件的多个存储器被并入到SOC中。 存储测试设置数据的pBIST只读存储器被组织以消除类似的嵌入式存储器的测试设置数据的多个实例。

公开(公告)号：US20150006820A1

公开(公告)日：2015-01-01

申请号：US13973306

申请日：2013-08-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Joseph Raymond Michael Zbiciak ,  Raguram Damodaran ,  Abhijeet Ashok Chachad

IPC: G06F12/08

CPC classification number: G06F12/0811

Abstract: Traffic output from a cache write-miss buffer is controlled by determining whether a predetermined condition is satisfied, and outputting an oldest entry from the buffer only in response to a determination that the predetermined condition is satisfied. Posting of a new entry to the buffer is insufficient to satisfy the predetermined condition.

Abstract translation: 通过确定是否满足预定条件来控制来自高速缓存写入 - 未命中缓冲器的流量输出，并且仅响应于满足预定条件的确定从缓冲器输出最旧的条目。 向缓冲器发送新条目不足以满足预定条件。

公开(公告)号：US20140164854A1

公开(公告)日：2014-06-12

申请号：US13709168

申请日：2012-12-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Raguram Damodaran ,  Naveen Bhoria ,  Aman Kokrady

IPC: G11C29/12

CPC classification number: G11C29/12 ,  G11C5/147 ,  G11C29/12005 ,  G11C29/16 ,  G11C2029/0401

Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories may be operating at a voltage domain different from the voltage domain of the pBIST. A plurality of buffer and synchronizing registers are used to avoid meta stable conditions caused by the time delays introduced by the voltage shifters required to bridge the various voltage domains.

Abstract translation: 用于测试嵌入式存储器的可编程内建自测（pBIST）系统，其中存储器可能在不同于pBIST的电压域的电压域上工作。 使用多个缓冲器和同步寄存器来避免由桥接各个电压域所需的电压移位器引入的时间延迟引起的元稳定条件。

公开(公告)号：US20250094358A1

公开(公告)日：2025-03-20

申请号：US18966252

申请日：2024-12-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Timothy David Anderson ,  Pete Michael Hippleheuser

IPC: G06F12/128 ,  G06F9/30 ,  G06F9/54 ,  G06F11/10 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0853 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1027 ,  G06F12/12 ,  G06F12/121 ,  G06F12/126 ,  G06F12/127 ,  G06F13/16 ,  G06F15/80 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C29/42 ,  G11C29/44

Abstract: Methods, apparatus, systems and articles of manufacture to reduce bank pressure using aggressive write merging are disclosed. An example apparatus includes a first cache storage; a second cache storage; a store queue coupled to at least one of the first cache storage and the second cache storage and operable to: receive a first memory operation; process the first memory operation for storing the first set of data in at least one of the first cache storage and the second cache storage; receive a second memory operation; and prior to storing the first set of data in the at least one of the first cache storage and the second cache storage, merge the first memory operation and the second memory operation.

公开(公告)号：US12242852B2

公开(公告)日：2025-03-04

申请号：US18353170

申请日：2023-07-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Dheera Balasubramanian Samudrala ,  Duc Bui ,  Rama Venkatasubramanian

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/445 ,  G06F12/02 ,  G06F16/31 ,  G06F16/41 ,  G06F16/901 ,  G11C11/409 ,  G06F3/06 ,  G06F9/355 ,  G06F12/0811

Abstract: A digital data processor includes an instruction memory storing instructions specifying a data processing operation and a data operand field, an instruction decoder coupled to the instruction memory for recalling instructions from the instruction memory and determining the operation and the data operand, and an operational unit coupled to a data register file and to an instruction decoder to perform a data processing operation upon an operand corresponding to an instruction decoded by the instruction decoder and storing results of the data processing operation. The operational unit is configured to perform a table write in response to a look up table initialization instruction by duplicating at least one data element from a source data register to create duplicated data elements, and writing the duplicated data elements to a specified location in a specified number of at least one table and a corresponding location in at least one other table.

公开(公告)号：US12216591B2

公开(公告)日：2025-02-04

申请号：US18477674

申请日：2023-09-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Timothy David Anderson ,  Pete Michael Hippleheuser

IPC: G06F12/128 ,  G06F9/30 ,  G06F9/54 ,  G06F11/10 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0853 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/121 ,  G06F12/126 ,  G06F12/127 ,  G06F13/16 ,  G06F15/80 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C29/42 ,  G11C29/44

Abstract: Methods, apparatus, systems and articles of manufacture to facilitate atomic compare and swap in cache for a coherent level 1 data cache system are disclosed. An example system includes a cache storage; a cache controller coupled to the cache storage wherein the cache controller is operable to: receive a memory operation that specifies a key, a memory address, and a first set of data; retrieve a second set of data corresponding to the memory address; compare the second set of data to the key; based on the second set of data corresponding to the key, cause the first set of data to be stored at the memory address; and based on the second set of data not corresponding to the key, complete the memory operation without causing the first set of data to be stored at the memory address.

公开(公告)号：US20250028645A1

公开(公告)日：2025-01-23

申请号：US18907746

申请日：2024-10-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Timothy David Anderson ,  Pete Michael Hippleheuser

IPC: G06F12/0891 ,  G06F12/1027

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to forward and invalidate inflight data in a store queue. An example apparatus includes a cache storage, a cache controller coupled to the cache storage and operable to receive a first memory operation, determine that the first memory operation corresponds to a read miss in the cache storage, determine a victim address in the cache storage to evict in response to the read miss, issue a read-invalidate command that specifies the victim address, compare the victim address to a set of addresses associated with a set of memory operations being processed by the cache controller, and in response to the victim address matching a first address of the set of addresses corresponding to a second memory operation of the set of memory operations, provide data associated with the second memory operation.

公开(公告)号：US12189540B2

公开(公告)日：2025-01-07

申请号：US18456619

申请日：2023-08-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Timothy David Anderson ,  Pete Michael Hippleheuser

IPC: G06F12/12 ,  G06F9/30 ,  G06F9/54 ,  G06F11/10 ,  G06F12/00 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0853 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/121 ,  G06F12/126 ,  G06F12/127 ,  G06F12/128 ,  G06F13/16 ,  G06F15/80 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C29/42 ,  G11C29/44

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to facilitate fully pipelined read-modify-write support in level 1 data cache using store queue and data forwarding. An example apparatus includes a first storage, a second storage, a store queue coupled to the first storage and the second storage, the store queue operable to receive a first memory operation specifying a first set of data, process the first memory operation for storing the first set of data in at least one of the first storage and the second storage, receive a second memory operation, and prior to storing the first set of data in the at least one of the first storage and the second storage, feedback the first set of data for use in the second memory operation.