公开(公告)号：US12094942B2

公开(公告)日：2024-09-17

申请号：US17815089

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L21/285 ,  H01L21/321 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/535 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/28568 ,  H01L21/3212 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5283 ,  H01L23/535 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor structure includes a metal gate structure (MG) formed over a substrate, a first gate spacer formed on a first sidewall of the MG, a second gate spacer formed on a second sidewall of the MG opposite to the first sidewall, where the second gate spacer is shorter than the first gate spacer, a source/drain (S/D) contact (MD) adjacent to the MG, where a sidewall of the MD is defined by the second gate spacer, and a contact feature configured to electrically connect the MG to the MD.

公开(公告)号：US12080646B2

公开(公告)日：2024-09-03

申请号：US18446113

申请日：2023-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L23/528 ,  H01L21/768 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L23/5283 ,  H01L21/76883 ,  H01L21/76892 ,  H01L29/401 ,  H01L29/41775 ,  H01L21/76885

Abstract: A method having a semiconductor substrate received and a first dielectric layer is formed over the semiconductor substrate. A trench is formed in the first dielectric layer. The trench is filled to form a conductive layer in the first dielectric layer. The conductive layer is segmented to form a first conductive feature and a second conductive feature separated from each other by a recess. The recess is filled with a second dielectric layer, such that one or both of the conductive features are end-capped by a portion of the first dielectric layer and a portion of the second dielectric layer.

公开(公告)号：US12009394B2

公开(公告)日：2024-06-11

申请号：US18083792

申请日：2022-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L21/02 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/02236 ,  H01L21/02603 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78696

Abstract: A device includes a device layer comprising a first transistor and a second transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure comprising a first dielectric layer on the backside of the device layer, wherein a semiconductor material is disposed between the first dielectric layer and a first source/drain region of the first transistor; a contact extending through the first dielectric layer to a second source/drain region of the second transistor; and a first conductive line electrically connected to the second source/drain region of the second transistor through the contact.

公开(公告)号：US11955515B2

公开(公告)日：2024-04-09

申请号：US17815761

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chuan Chiu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Chih-Hao Wang ,  Huan-Chieh Su ,  Chun-Yuan Chen ,  Li-Zhen Yu ,  Yu-Ming Lin

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/423

CPC classification number: H01L29/0673 ,  H01L21/823418 ,  H01L29/42392

Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.

公开(公告)号：US11916133B2

公开(公告)日：2024-02-27

申请号：US17676699

申请日：2022-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Lin-Yu Huang ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/768

CPC classification number: H01L29/6656 ,  H01L21/76832 ,  H01L21/76834 ,  H01L29/66545

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a gate structure sandwiched between and in contact with a first spacer feature and a second spacer feature, a top surface of the first spacer feature and a top surface of the second spacer feature extending above a top surface of the gate structure, a gate self-aligned contact (SAC) dielectric feature over the first spacer feature and the second spacer feature, a contact etch stop layer (CESL) over the gate SAC dielectric feature, a dielectric layer over the CESL, a gate contact feature extending through the dielectric layer, the CESL, the gate SAC dielectric feature, and between the first spacer feature and the second spacer feature to be in contact with the gate structure, and a liner disposed between the first spacer feature and the gate contact feature.

公开(公告)号：US20240021707A1

公开(公告)日：2024-01-18

申请号：US18364574

申请日：2023-08-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Lin-Yu Huang ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/768

CPC classification number: H01L29/6656 ,  H01L21/76832 ,  H01L21/76834 ,  H01L29/66545

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a gate structure sandwiched between and in contact with a first spacer feature and a second spacer feature, a top surface of the first spacer feature and a top surface of the second spacer feature extending above a top surface of the gate structure, a gate self-aligned contact (SAC) dielectric feature over the first spacer feature and the second spacer feature, a contact etch stop layer (CESL) over the gate SAC dielectric feature, a dielectric layer over the CESL, a gate contact feature extending through the dielectric layer, the CESL, the gate SAC dielectric feature, and between the first spacer feature and the second spacer feature to be in contact with the gate structure, and a liner disposed between the first spacer feature and the gate contact feature.

公开(公告)号：US20230386905A1

公开(公告)日：2023-11-30

申请号：US18446183

申请日：2023-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hao Chang ,  Lin-Yu Huang ,  Li-Zhen Yu ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L21/768 ,  H01L21/76 ,  H01L23/528 ,  H01L23/532 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L21/7682 ,  H01L21/76 ,  H01L21/76834 ,  H01L23/5286 ,  H01L23/53295 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/78696 ,  H01L21/02172

Abstract: A semiconductor structure includes first and second epitaxial features, at least one semiconductor channel layer connecting the first and second epitaxial features, and a gate structure engaging the semiconductor channel layer. The first and second epitaxial features, the semiconductor channel layer, and the gate structure are at a frontside of the semiconductor structure. The semiconductor structure also includes a backside metal wiring layer at a backside of the semiconductor structure, and a backside conductive contact electrically connecting the first epitaxial feature to the backside metal wiring layer. The backside metal wiring layer is spaced away from the gate structure with an air gap therebetween.

公开(公告)号：US11804486B2

公开(公告)日：2023-10-31

申请号：US17572212

申请日：2022-01-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Huan-Chieh Su ,  Li-Zhen Yu ,  Chun-Yuan Chen ,  Shih-Chuan Chiu ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L21/027 ,  H01L21/308 ,  H01L21/306

CPC classification number: H01L27/0886 ,  H01L21/0274 ,  H01L21/3086 ,  H01L21/30604

Abstract: A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.

公开(公告)号：US11798884B2

公开(公告)日：2023-10-24

申请号：US17682884

申请日：2022-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L21/3213

CPC classification number: H01L23/5283 ,  H01L21/32139 ,  H01L21/76885 ,  H01L23/5226

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes an active region including a channel region and a source/drain region and extending along a first direction, and a source/drain contact structure over the source/drain region. The source/drain contact structure includes a base portion extending lengthwise along a second direction perpendicular to the first direction, and a via portion over the base portion. The via portion tapers away from the base portion.

公开(公告)号：US20230326983A1

公开(公告)日：2023-10-12

申请号：US18329126

申请日：2023-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/28 ,  H01L21/8234 ,  H01L29/417

CPC classification number: H01L29/41725 ,  H01L21/28097 ,  H01L21/28158 ,  H01L21/823475

Abstract: A device includes a substrate, an isolation structure over the substrate, a gate structure over the isolation structure, a gate spacer on a sidewall of the gate structure, a source/drain (S/D) region adjacent to the gate spacer, a silicide on the S/D region, a dielectric liner over a sidewall of the gate spacer and on a top surface of the isolation structure, wherein a bottom surface of the dielectric liner is above a top surface of the silicide layer and spaced away from the top surface of the silicide layer in a cross-sectional plane perpendicular to a lengthwise direction of the gate structure.