公开(公告)号：US10164012B2

公开(公告)日：2018-12-25

申请号：US15064402

申请日：2016-03-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ka-Hing Fung ,  Kuo-Cheng Ching ,  Ying-Keung Leung

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/306 ,  H01L21/02 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor device includes first channel layers disposed over a substrate, a first source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the first channel layers, a gate electrode layer disposed on the gate dielectric layer and wrapping each of the first channel layers, and a liner semiconductor layer disposed between the first channel layers and the first source/drain region.

公开(公告)号：US10115823B2

公开(公告)日：2018-10-30

申请号：US15409014

申请日：2017-01-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Ching-Wei Tsai ,  Wai-Yi Lien

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/51 ,  H01L29/16 ,  H01L21/02 ,  H01L21/762 ,  H01L29/06 ,  H01L29/165

Abstract: A method for manufacturing a semiconductor device includes forming a fin structure including a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. An isolation insulating layer is formed so that the channel layer of the fin structure protrudes from the isolation insulating layer and a part of or an entirety of the oxide layer is embedded in the isolation insulating layer. A gate structure is formed over the fin structure. A recessed portion is formed by etching a part of the fin structure not covered by the gate structure such that the oxide layer is exposed. A recess is formed in the exposed oxide layer. An epitaxial seed layer in the recess in the oxide layer. An epitaxial layer is formed in and above the recessed portion. The epitaxial layer is in contact with the epitaxial seed layer.

公开(公告)号：US10026737B1

公开(公告)日：2018-07-17

申请号：US15491206

申请日：2017-04-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Chih-Liang Chen ,  Shi Ning Ju

IPC: H01L21/00 ,  H01L21/8238 ,  H01L21/336 ,  H01L27/148 ,  H01L29/76 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/06

Abstract: In a method of manufacturing a semiconductor device, a separation wall made of a dielectric material is formed between two fin structures. A dummy gate structure is formed over the separation wall and the two fin structures. An interlayer dielectric (ILD) layer is formed over the dummy gate structure. An upper portion of the ILD layer is removed, thereby exposing the dummy gate structure. The dummy gate structure is replaced with a metal gate structure. A planarization operation is performed to expose the separation wall, thereby dividing the metal gate structure into a first gate structure and a second gate structure. The first gate structure and the second gate structure are separated by the separation wall.

公开(公告)号：US20170338225A1

公开(公告)日：2017-11-23

申请号：US15226007

申请日：2016-08-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Shi-Ning Ju ,  Chih-Hao Wang ,  Ying-Keung Leung ,  Carlos H. Diaz

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/108 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure includes a substrate, at least one active fin present on the substrate, and at least one isolation dielectric surrounding the active fin. The isolation dielectric has at least one trench therein. The semiconductor structure further includes at least one dielectric liner present on at least one sidewall of the trench of the isolation dielectric, and at least one filling dielectric present in the trench of the isolation dielectric.

公开(公告)号：US09761723B2

公开(公告)日：2017-09-12

申请号：US14592591

申请日：2015-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Kuo-Cheng Ching

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/423 ,  H01L29/165

CPC classification number: H01L29/7851 ,  H01L21/02236 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a fin channel structure over the semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin channel structure. The semiconductor device structure further includes a source/drain structure adjacent to the fin channel structure and a doped region between the semiconductor substrate and the fin channel structure. In addition, the semiconductor device structure includes a blocking layer between the fin channel structure and the doped region.

公开(公告)号：US20150054039A1

公开(公告)日：2015-02-26

申请号：US13970790

申请日：2013-08-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Zhi-Chang Lin ,  Chao Hsiung Wang ,  Chi-Wen Liu

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/76

CPC classification number: H01L29/785 ,  H01L21/76 ,  H01L21/76229 ,  H01L29/66795

Abstract: The present disclosure relates to a Fin field effect transistor (FinFET) device having epitaxial enhancement structures, and an associated method of fabrication. In some embodiments, the FinFET device has a semiconductor substrate having a plurality of isolation regions overlying the semiconductor substrate. A plurality of three-dimensional fins protrude from a top surface of the semiconductor substrate at locations between the plurality of isolation regions. Respective three-dimensional fins have an epitaxial enhancement structure that introduces a strain into the three-dimensional fin. The epitaxial enhancement structures are disposed over a semiconductor material within the three-dimensional fin at a position that is more than 10 nanometers above a bottom of an adjacent isolation region. Forming the epitaxial enhancement structure at such a position provides for sufficient structural support to avoid isolation region collapse.

Abstract translation: 本公开涉及具有外延增强结构的Fin场效应晶体管（FinFET）器件及其相关制造方法。 在一些实施例中，FinFET器件具有半导体衬底，其具有覆盖半导体衬底的多个隔离区域。 在多个隔离区域之间的位置处，多个三维翅片从半导体衬底的顶表面突出。 相应的三维翅片具有向三维翅片引入应变的外延增强结构。 外延增强结构被布置在三维鳍片内的半导体材料上方，位于相邻隔离区域的底部之上超过10纳米的位置。 在这样的位置形成外延增强结构提供足够的结构支撑以避免隔离区域崩溃。

公开(公告)号：US08823060B1

公开(公告)日：2014-09-02

申请号：US13771249

申请日：2013-02-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jean-Pierre Colinge ,  Kuo-Cheng Ching

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7843 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: FinFETs in which a swelled material within the fin, typically an oxide of the fin semiconductor, causes strain that significantly increases charge carrier mobility within the FinFET channel. The concept can be applied to either p-type or n-type FinFETs. For p-type FinFETs the swelled material is positioned underneath the source and drain regions. For n-type FinFETs the swelled material is positioned underneath the channel region. The swelled material can be used with or without strain-inducing epitaxy on the source and drain areas and can provide greater strain than is achievable by strain-inducing epitaxy alone.

Abstract translation: 翅片内部的膨胀材料（通常为散热片半导体的氧化物）的FinFET导致在FinFET通道内显着增加电荷载流子迁移率的应变。 该概念可以应用于p型或n型FinFET。 对于p型FinFET，膨胀材料位于源极和漏极区域的下方。 对于n型FinFET，膨胀的材料位于通道区域的下方。 溶胀材料可以在源极和漏极区域具有或不具有应变诱导外延使用，并且可以提供比单独应变诱导外延可实现的更大的应变。

公开(公告)号：US12278236B2

公开(公告)日：2025-04-15

申请号：US18444356

申请日：2024-02-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Shi-Ning Ju ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/027 ,  H01L21/033 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/08 ,  H01L29/165 ,  H01L29/205 ,  H01L29/267 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes first and second semiconductive fins, a first dielectric layer, a first gate structure, a spacer layer, and an oxide material. The first dielectric layer is laterally between the first and second semiconductive fins. From a cross-sectional view taken along a direction perpendicular to a lengthwise direction of the first semiconductive fin, the first dielectric layer has a U-shaped profile. The first gate structure extends across the first and second semiconductive fins and the first dielectric layer. The spacer layer underlies the first dielectric layer and further extends to laterally surround a lower portion of the first dielectric layer, a lower portion of the first semiconductive fin, and a lower portion of the second semiconductive fin. The oxide material is nested in the first dielectric layer. A top surface of the oxide material is at an elevation higher than a top surface of the spacer layer.

公开(公告)号：US12266654B2

公开(公告)日：2025-04-01

申请号：US16215676

申请日：2018-12-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Huan-Chieh Su ,  Mao-Lin Huang ,  Zhi-Chang Lin

IPC: H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49

Abstract: Provided are FinFET devices and methods of forming the same. A FinFET device includes a substrate, a metal gate strip, gate spacers and a dielectric helmet. The substrate has fins. The metal gate strip is disposed across the fins and has a reversed T-shaped portion between two adjacent fins. The gate spacers are disposed on opposing sidewalls of the metal gate strip. A dielectric helmet is disposed over the metal gate strip.

公开(公告)号：US12191307B2

公开(公告)日：2025-01-07

申请号：US17654804

申请日：2022-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: A method for fabricating a semiconductor device includes providing a fin in a first region of a substrate. The fin includes a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. A portion of a layer of the second type of epitaxial layers in a channel region of the first fin is removed to form a first gap between a first layer of the first type of epitaxial layers and a second layer of the first type of epitaxial layers. A first portion of a first gate structure is formed within the first gap and extending from a first surface of the first layer of the first type of epitaxial layers to a second surface of the second layer of the first type of epitaxial layers. A first source/drain feature is formed abutting the first portion of the first gate structure.