公开(公告)号：US20220352208A1

公开(公告)日：2022-11-03

申请号：US17868278

申请日：2022-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin ,  Chi On Chui

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L29/78 ,  H01L21/28 ,  H01L27/1159 ,  H01L27/11585 ,  H01L29/786

Abstract: A method includes forming a stack of multi-layers, each multi-layer including a first isolation layer, a semiconductor layer, and a first metal layer; etching the stack of multi-layers to form gate trenches in a channel region; removing the first isolation layers and the first metal layers from the channel region, resulting in channel portions of the semiconductor layers exposed in the gate trenches; laterally recessing the first metal layers from the gate trenches, resulting in gaps between adjacent layers of the first isolation layers and the semiconductor layers; forming an inner spacer layer in the gaps; forming a ferroelectric (FE) layer surrounding each of the channel portions and over sidewalls of the gate trenches, wherein the inner spacer layer is disposed laterally between the FE layer and the first metal layers; and depositing a metal gate layer over the FE layer and filling the gate trenches.

公开(公告)号：US20220344402A1

公开(公告)日：2022-10-27

申请号：US17238678

申请日：2021-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chenchen Jacob Wang ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Chi On Chui

IPC: H01L27/22 ,  H01L29/24 ,  H01L21/02 ,  H01L43/12

Abstract: In an embodiment, a semiconductor device includes a first dielectric layer over a substrate and a first access transistor and a second access transistor in a memory cell of a memory array, the first access transistor and the second access transistor each including a bottom electrode in the first dielectric layer, a conductive gate in a second dielectric layer, where the second dielectric layer is over the bottom electrode and the first dielectric layer, a channel region extending through the conductive gate to contact the bottom electrode, and a top electrode over the channel region.

公开(公告)号：US11482595B1

公开(公告)日：2022-10-25

申请号：US17238983

申请日：2021-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chuan Chiu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Chih-Hao Wang ,  Huan-Chieh Su ,  Chun-Yuan Chen ,  Li-Zhen Yu ,  Yu-Ming Lin

IPC: H01L29/06 ,  H01L29/423 ,  H01L21/8234

Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.

公开(公告)号：US20220310132A1

公开(公告)日：2022-09-29

申请号：US17842256

申请日：2022-06-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chenchen Jacob Wang ,  Yi-Ching Liu ,  Han-Jong Chia ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Yih Wang

IPC: G11C5/06 ,  H01L27/11587 ,  H01L29/78 ,  H01L27/11597 ,  H01L29/24 ,  H01L27/11585 ,  H01L27/11556 ,  H01L29/786

Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a ferroelectric (FE) material contacting a first word line; an oxide semiconductor (OS) layer contacting a source line and a bit line, the FE material being disposed between the OS layer and the first word line; a dielectric material contacting the FE material, the FE material being between the dielectric material and the first word line; an inter-metal dielectric (IMD) over the first word line; a first contact extending through the IMD to the first word line, the first contact being electrically coupled to the first word line; a second contact extending through the dielectric material and the FE material; and a first conductive line electrically coupling the first contact to the second contact.

公开(公告)号：US11443987B2

公开(公告)日：2022-09-13

申请号：US16888217

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Huan-Chieh Su ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L23/528 ,  H01L21/764 ,  H01L21/3105 ,  H01L21/02 ,  H01L29/417

Abstract: A method includes providing a structure having transistors, an isolation structure over the transistors, metal plugs through the isolation structure and connecting to the transistors, and a trench with the isolation structure and the metal plugs as sidewalls. The method further includes forming a dielectric liner on the sidewalls of the trench and over the isolation structure and the metal plugs. The dielectric liner is thicker at an opening portion of the trench than at another portion of the trench so that an air gap is formed inside the trench and the air gap is surrounded by the dielectric liner. The method further includes depositing a sacrificial layer over the dielectric liner and over the air gap and performing CMP to remove the sacrificial layer and to recess the dielectric liner until the isolation structure and the metal plugs are exposed. The air gap remains inside the trench.

公开(公告)号：US20220285519A1

公开(公告)日：2022-09-08

申请号：US17319461

申请日：2021-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Rainer Yen-Chieh Huang ,  Hai-Ching Chen ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L29/51 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66

Abstract: The present disclosure relates to an integrated circuit (IC) chip including a memory cell with a carrier barrier layer for threshold voltage tunning. The memory cell may, for example, include a gate electrode, a ferroelectric structure, and a semiconductor structure. The semiconductor structure is vertically stacked with the gate electrode and the ferroelectric structure, and the ferroelectric structure is between the gate electrode and the semiconductor structure. A pair of source/drain electrodes is laterally separated and respectively on opposite sides of the gate electrode, and a carrier barrier layer separates the source/drain electrodes from the semiconductor structure.

公开(公告)号：US11361986B2

公开(公告)日：2022-06-14

申请号：US16808902

申请日：2020-03-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Cheng-Chi Chuang ,  Chih-Hao Wang ,  Yu-Ming Lin ,  Lin-Yu Huang

IPC: H01L21/768 ,  H01L23/522 ,  H01L29/66 ,  H01L29/417

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a substrate, a first contact layer, and a gate electrode. The first contact layer overlies the substrate and the gate electrode overlies the substrate and is laterally spaced from the first contact layer. A first spacer structure surrounds outermost sidewalls of the first contact layer and separates the gate electrode from the first contact layer. A first hard mask structure is arranged over the first contact layer and is between portions of the first spacer structure. A first contact via extends through the first hard mask structure and contacts the first contact layer. A first liner layer is arranged directly between the first hard mask structure and the first spacer structure.

公开(公告)号：US11355387B2

公开(公告)日：2022-06-07

申请号：US16730367

申请日：2019-12-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Chuan You ,  Chia-Hao Chang ,  Wai-Yi Lien ,  Yu-Ming Lin

IPC: H01L21/768 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/28 ,  H01L23/485 ,  H01L29/417

Abstract: A method includes forming a dummy gate stack over a substrate; forming a gate spacer on a sidewall of the dummy gate stack; after forming the gate spacer, forming a source/drain region in the substrate and adjacent to the gate spacer; forming a first interlayer dielectric layer over the source/drain region and adjacent to the gate spacer; replacing the dummy gate stack with a metal gate stack; forming a protective layer over the metal gate stack and the gate spacer; after forming the protective layer, removing the first interlayer dielectric layer to expose a sidewall of the gate spacer and a sidewall of the protective layer; and forming a bottom conductive feature over the source/drain region.

公开(公告)号：US20220157721A1

公开(公告)日：2022-05-19

申请号：US17665941

申请日：2022-02-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L23/528 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66 ,  H01L21/311 ,  H01L21/321 ,  H01L21/768 ,  H01L29/78 ,  H01L21/3205 ,  H01L23/522

Abstract: A method of forming a semiconductor structure includes first forming a metal gate (MG) over a semiconductor layer, a gate spacer on a sidewall of the MG, and a source/drain (S/D) feature disposed in the semiconductor layer and adjacent to the MG, forming an S/D contact (MD) over the S/D feature, forming a first ILD layer over the MG and the MD, and subsequently patterning the first ILD layer to form an opening. The method further includes forming a metal layer in the opening, such that the metal layer contacts both the MG and the MD, removing a top portion of the metal layer to form a trench, filling the trench with a dielectric layer, and subsequently forming a second ILD layer over the dielectric layer.

公开(公告)号：US11222892B2

公开(公告)日：2022-01-11

申请号：US16901963

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh Su ,  Li-Zhen Yu ,  Chun-Yuan Chen ,  Shih-Chuan Chiu ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L21/027 ,  H01L21/308 ,  H01L21/306

Abstract: A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.