公开(公告)号：US07035959B2

公开(公告)日：2006-04-25

申请号：US09835824

申请日：2001-04-17

申请人： Satoshi Umezu ,  Jun Miyajima ,  Takahiro Yamaguchi ,  Norio Arakawa

发明人： Satoshi Umezu ,  Jun Miyajima ,  Takahiro Yamaguchi ,  Norio Arakawa

IPC分类号： G06F13/36

CPC分类号： H04L41/00 ,  G01R31/2834 ,  G01R31/31907 ,  H04Q9/00 ,  H04Q9/04

摘要： A measuring device, a measuring device controller, a measuring system, a measurement process performing method and a recording medium thereof which can easily and adequately perform a measurement process are provided. The present invention is constructed to include a program receiving unit 110 for receiving a control program, which comprises contents prescribing a measurement process, from said network; a memorizing unit 120 for memorizing the control program; an initiating instruction receiving unit 130 for receiving a program initiating instruction of the control program from the network; and a measurement control unit 156 for letting a measuring unit 160 perform the measurement process based on the control program memorized by the memorizing unit 120 in case the initiating instruction receiving unit 130 receives the program initiating instruction.

公开(公告)号：US07031595B2

公开(公告)日：2006-04-18

申请号：US09905882

申请日：2001-07-17

申请人： Takahiro Yamaguchi

发明人： Takahiro Yamaguchi

IPC分类号： H04N5/91

CPC分类号： G11B27/28 ,  G11B27/105 ,  G11B2220/2562 ,  H04N5/783 ,  H04N5/85

摘要： A disc reproducing apparatus which reproduces images recorded on an optical disc has: scene detecting means for detecting scenes with judging, as a leading frame of a scene, a frame which is abnormally biased to one of future and past time directions of predictive coding of B-pictures; scene reproduction controlling means for, each time when a predetermined time period which is preset elapses, reproducing images of the scenes which are detected by the scene detecting means, for a predetermined time period which is preset; and timer controlling means for measuring and controlling the time periods.

公开(公告)号：US20060031732A1

公开(公告)日：2006-02-09

申请号：US11238822

申请日：2005-09-28

申请人： Masahiro Ishida ,  Takahiro Yamaguchi

发明人： Masahiro Ishida ,  Takahiro Yamaguchi

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G01R31/2882 ,  G01R31/31813 ,  G01R31/3183 ,  G01R31/318328 ,  G01R31/31917 ,  G06F11/263

摘要： A test pattern sequence which is used to test a delay fault or an open fault which accompanies a delay occurring in an IC is easily and rapidly generated. A list of locations such as logic gates and signal lines within the circuit where a fault is likely to occur is prepared (101). One of the faults is selected, and an initialization test pattern v1 which establishes an initial value for activating the fault at the location of a fault is determined by the implication operation (103), and a propagation test pattern v2 which causes a stuck-at fault to be propagated to a following gate is determined by the implication operation (105). A sequence formed by v1 and v2 is registered with a test pattern list (107), and the described operations are repeated until there remains no unprocessed fault in the fault list.

公开(公告)号：US20060017101A1

公开(公告)日：2006-01-26

申请号：US11182026

申请日：2005-07-15

申请人： Tadahiro Ohmi ,  Koji Kotani ,  Kazuyuki Maruo ,  Takahiro Yamaguchi

发明人： Tadahiro Ohmi ,  Koji Kotani ,  Kazuyuki Maruo ,  Takahiro Yamaguchi

IPC分类号： H01L29/76

CPC分类号： H01L27/12 ,  H01L21/8221 ,  H01L27/0688 ,  Y10S257/903

摘要： There is provided a small-type semiconductor integrated circuit whose circuit area is small and whose wiring length is short. The semiconductor integrated circuit is constructed in a multi-layer structure and is provided with a first semiconductor layer, a first semiconductor layer transistor formed in the first semiconductor layer, a wiring layer which is deposited on the first semiconductor layer and in which metal wires are formed, a second semiconductor layer deposited on the wiring layer and a second semiconductor layer transistor formed in the second semiconductor layer. It is noted that insulation of a gate insulating film of the first semiconductor layer transistor is almost equal with that of a gate insulating film of the second semiconductor layer transistor and the gate insulating film of the second semiconductor layer transistor is formed by means of radical oxidation or radical nitridation.

摘要翻译： 提供电路面积小，布线长度短的小型半导体集成电路。 半导体集成电路构造为多层结构，并且设置有第一半导体层，形成在第一半导体层中的第一半导体层晶体管，布置在第一半导体层上并且其中金属线为 形成，沉积在布线层上的第二半导体层和形成在第二半导体层中的第二半导体层晶体管。 注意，第一半导体层晶体管的栅极绝缘膜的绝缘几乎等于第二半导体层晶体管的栅极绝缘膜的绝缘，并且通过自由基氧化形成第二半导体层晶体管的栅极绝缘膜 或自由基氮化。

公开(公告)号：US20050267696A1

公开(公告)日：2005-12-01

申请号：US10925870

申请日：2004-08-25

申请人： Takahiro Yamaguchi ,  Masahiro Ishida ,  Mani Soma

发明人： Takahiro Yamaguchi ,  Masahiro Ishida ,  Mani Soma

IPC分类号： G01R29/02 ,  G01R29/027 ,  G01R29/26 ,  G01R31/317 ,  G01R31/319 ,  G01R31/3193 ,  H04L1/20 ,  G01R15/00

CPC分类号： G01R31/31709 ,  G01R29/02 ,  G01R29/0273 ,  G01R29/26 ,  G01R31/31922 ,  G01R31/31937 ,  H04L1/203 ,  H04L1/205

摘要： A measuring apparatus for measuring reliability against jitter of an electronic device, including: a jitter tolerance estimator operable to estimate a jitter tolerance of the electronic device based on an output signal output from the electronic device according to an input signal input through a transmission line of which the transmission length is shorter than a predetermined length so that it does not generate a deterministic jitter; a jitter tolerance degradation quantity estimator operable to estimate a quantity of degradation of the jitter tolerance which deteriorates by the deterministic jitter caused in the input signal by transmission through the long transmission line when the input signal is input into the electronic device through the transmission line, of which the transmission length is longer than a predetermined length so that it may cause the deterministic jitter; a system jitter tolerance estimator operable to estimate a jitter tolerance of the electronic device and a jitter tolerance of a system including the long transmission line and the electronic device based on quantity of degradation of the jitter tolerance, is provided.

摘要翻译： 一种用于测量电子设备抖动的可靠性的测量装置，包括：抖动容限估计器，用于根据从电子设备输出的输出信号，根据通过传输线输入的输入信号来估计电子设备的抖动容限 其传输长度短于预定长度，使得其不产生确定性抖动; 抖动容忍劣化量估计器，用于当通过传输线路将输入信号输入到电子设备中时，通过传输通过长传输线路来估计在输入信号中产生的确定性抖动而导致的抖动容差劣化的数量， 其传输长度大于预定长度，从而可能导致确定性抖动; 提供了一种用于估计电子设备的抖动容限的系统抖动容限估计器，以及基于抖动容限的劣化量的包括长传输线路和电子设备的系统的抖动容限。

公开(公告)号：US20050129104A1

公开(公告)日：2005-06-16

申请号：US10824763

申请日：2004-04-14

申请人： Masahiro Ishida ,  Takahiro Yamaguchi ,  Mani Soma

发明人： Masahiro Ishida ,  Takahiro Yamaguchi ,  Mani Soma

IPC分类号： G01R29/02 ,  G01R31/28 ,  G01R31/3167 ,  G01R31/317 ,  G01R31/319 ,  G01R31/3193 ,  H04Q1/20

CPC分类号： G01R31/31709 ,  G01R31/31922 ,  G01R31/31937

摘要： A testing device for testing an electronic device is provided. The testing device includes: a deterministic jitter application unit for applying deterministic jitter to a given input signal without causing an amplitude modulation component and supplying the input signal with the deterministic jitter to the electronic device; a jitter amount controller for controlling the magnitude of the deterministic jitter generated by the deterministic jitter application unit; and a determination unit for determining whether or not the electronic device is defective based on an output signal output from the electronic device in accordance with the input signal.

摘要翻译： 提供了一种用于测试电子设备的测试设备。 测试设备包括：确定性抖动应用单元，用于将确定性抖动应用于给定的输入信号，而不引起幅度调制分量，并向电子设备提供具有确定性抖动的输入信号; 抖动量控制器，用于控制由确定性抖动施加单元产生的确定性抖动的大小; 以及确定单元，用于基于根据输入信号从电子设备输出的输出信号来确定电子设备是否有故障。

公开(公告)号：US06905321B2

公开(公告)日：2005-06-14

申请号：US10453623

申请日：2003-06-04

申请人： Kazunori Uchiyama ,  Naoki Hakamada ,  Takahiro Yamaguchi ,  Takashi Satou

发明人： Kazunori Uchiyama ,  Naoki Hakamada ,  Takahiro Yamaguchi ,  Takashi Satou

IPC分类号： B60T17/00 ,  B60T8/40 ,  B60T8/48 ,  F04C2/10 ,  F04C15/00 ,  F04C18/00

CPC分类号： F04C15/0026 ,  B60T8/4031 ,  B60T8/4872 ,  F04C2/102

摘要： In a rotary pump for a braking apparatus, a discharge trench is formed on an axial direction end surface of a second side plate that forms a mechanical seal. As a result, rotors are pressed back toward a side of a first side plate by a discharge pressure of brake fluid channeled to the discharge trench. Accordingly, a force pressing the rotors toward the second side plate is reduced and frictional resistance is reduced.

摘要翻译： 在用于制动装置的旋转泵中，在形成机械密封的第二侧板的轴向端表面上形成排放沟槽。 结果，通过被引导到放电沟槽的制动液的排出压力将转子向第一侧板的侧面压回。 因此，使转子朝向第二侧板的力减小，摩擦阻力降低。

公开(公告)号：US06828815B2

公开(公告)日：2004-12-07

申请号：US10779905

申请日：2004-02-17

申请人： Masahiro Ishida ,  Takahiro Yamaguchi ,  Yoshihiro Hashimoto

发明人： Masahiro Ishida ,  Takahiro Yamaguchi ,  Yoshihiro Hashimoto

IPC分类号： G01R3126

CPC分类号： G01R31/3004 ,  G01R31/3181

摘要： A fault analysis method and apparatus which is able to improve the reliability of fault analysis of semiconductor integrated circuit. In case of supplying a test pattern sequence having a plurality of test patterns to the semiconductor IC, an analysis point whose electric potential changes according to the change of supplied test pattern is placed corresponding to the test pattern sequence. Then, a transient power supply current generated on the semiconductor IC according to the change of the test pattern is measured and determined whether the measured transient power supply current is abnormal or not. A defection point is presumed based on the test pattern sequence where the transient power supply current is abnormal, and the analysis point placed corresponding to the test pattern sequence.

摘要翻译： 一种能够提高半导体集成电路故障分析可靠性的故障分析方法和装置。 在向半导体IC提供具有多个测试图案的测试图案序列的情况下，根据所提供的测试图案的变化对其电位变化的分析点与测试图案序列相对应。 然后，测量根据测试图案的变化在半导体IC上产生的瞬态电源电流，并确定测量的瞬态电源电流是否异常。 基于瞬态电源电流异常的测试图案序列推测出缺点，并且对应于测试图案序列放置分析点。

公开(公告)号：US06775321B1

公开(公告)日：2004-08-10

申请号：US09703469

申请日：2000-10-31

申请人： Mani Soma ,  Masahiro Ishida ,  Takahiro Yamaguchi ,  Toshifumi Watanabe

发明人： Mani Soma ,  Masahiro Ishida ,  Takahiro Yamaguchi ,  Toshifumi Watanabe

IPC分类号： H04B1700

CPC分类号： G01R29/26

摘要： A signal under measurement is transformed into a complex analytic signal using Hilbert transformation to estimate an instantaneous phase of the signal under measurement from the complex analytic signal. A least mean square line of the instantaneous phase is calculated to obtain a linear instantaneous phase of the signal under measurement, and a zero-crossing timing of the signal under measurement is estimated using an interpolation method. Then a difference between the instantaneous phase and the linear instantaneous phase at the zero-crossing timing is calculated to estimate a timing jitter sequence. A jitter of the signal under measurement is obtained from the jitter sequence.

摘要翻译： 使用希尔伯特变换将测量信号转换成复数分析信号，以从复数分析信号估计测量信号的瞬时相位。 计算瞬时相位的最小均方根以获得测量信号的线性瞬时相位，并且使用内插方法估计测量信号的过零定时。 然后计算在过零时刻的瞬时相位和线性瞬时相位之间的差以估计定时抖动序列。 从抖动序列获得测量信号的抖动。

公开(公告)号：US06737852B2

公开(公告)日：2004-05-18

申请号：US10033188

申请日：2001-10-25

申请人： Mani Soma ,  Masahiro Ishida ,  Takahiro Yamaguchi

发明人： Mani Soma ,  Masahiro Ishida ,  Takahiro Yamaguchi

IPC分类号： G01R2302

CPC分类号： G01R31/31725

摘要： A clock skew measuring apparatus for measuring a clock skew between a plurality of clock signals to be measured in a device under test, includes: a clock signal selecting element for receiving clock signals and outputting them by selecting one of the clock signals one by one; and a clock skew estimator for receiving a reference signal input to the device under test and the clock signals to be measured selected by the clock signal selecting element one by one and for obtaining the clock skew between the clock signals to be measured.

摘要翻译： 一种时钟偏差测量装置，用于测量被测器件中要测量的多个时钟信号之间的时钟偏差，包括：时钟信号选择元件，用于接收时钟信号并通过逐个选择一个时钟信号来输出; 以及时钟偏差估计器，用于一个接一个地接收输入到被测器件的参考信号和由时钟信号选择元件选择的要被测量的时钟信号，并用于获得待测时钟信号之间的时钟偏差。