公开(公告)号：US20170047104A1

公开(公告)日：2017-02-16

申请号：US14824982

申请日：2015-08-12

申请人： Avalanche Technology, Inc.

发明人： Ebrahim Abedifard ,  Parviz Keshtbod

IPC分类号： G11C11/16 ,  G11C7/04 ,  G11C5/14

CPC分类号： G11C11/1675 ,  G11C5/147 ,  G11C7/04 ,  G11C11/1695 ,  G11C11/1697 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409

摘要： A non-volatile memory system includes a first circuit and a second circuit both coupled to a magnetoresistance tunnel junction (MTJ) cell to substantially reduce the level of current flowing through the MTJ with rise in temperature, as experienced by the MTJ. The first circuit is operable to adjust a slope of a curve representing current as a function of temperature and the second circuit is operable to adjust a value of the current level through the MTJ to maintain current constant or to reduce current when the temperature increases. This way sufficient current is provided for the MTJ at different temperatures, to prevent write failure, over programming, MTJ damage and waste of current.

摘要翻译： 非易失性存储器系统包括耦合到磁阻隧道结（MTJ）单元的第一电路和第二电路，以如MTJ所经历的那样大大降低流经MTJ的电流随温度升高的水平。 第一电路可操作以调节表示作为温度的函数的电流的曲线的斜率，并且第二电路可操作以通过MTJ调整电流电平的值以维持电流恒定或者当温度升高时减小电流。 这样可以在不同的温度下为MTJ提供足够的电流，以防止写入故障，超过编程，MTJ损坏和浪费电流。

公开(公告)号：US09569712B1

公开(公告)日：2017-02-14

申请号：US15166981

申请日：2016-05-27

申请人： International Business Machines Corporation

发明人： Anthony J. Annunziata ,  Chandrasekharan Kothandaraman ,  Philip L. Trouilloud

IPC分类号： G11C11/00 ,  G06K19/06 ,  G11C11/16 ,  H01L43/02 ,  H01L43/08 ,  H01L27/22

CPC分类号： H03K19/003 ,  G06F21/44 ,  G06K19/06196 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1695 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08

摘要： The present invention provides integrated circuit chips having chip identification aspects. The chips include magnetic tunnel junction (MTJ) structures, and more specifically, include permanent bit strings used for chip identification and/or authentication. Systems and processes for chip identification are also disclosed herein. The MTJ element structures provided herein can have a defined resistance profile such that the intrinsic variability of the MTJ element structure is used to encode and generate a bit string that becomes a fingerprint for the chip. In some embodiments, an oxygen treatment covering all or a selected portion of an array of MTJ elements can be used to create a mask or secret key that can be used and implemented to enhance chip identification.

公开(公告)号：US09443113B2

公开(公告)日：2016-09-13

申请号：US14942665

申请日：2015-11-16

申请人： Everspin Technologies, Inc.

发明人： Syed M. Alam ,  Thomas Andre

IPC分类号： G06F21/78 ,  G06F21/79 ,  G06F21/86 ,  G11C7/24 ,  G11C11/16 ,  G06F3/06

CPC分类号： G06F21/79 ,  G06F3/062 ,  G06F3/0653 ,  G06F3/0679 ,  G06F21/78 ,  G06F21/86 ,  G06F2221/2143 ,  G11C7/24 ,  G11C11/1695

摘要： In response to a tamper-attempt indication, a memory device selectively disables one or more memory operations. Disabling can be accomplished by different techniques, including altering bias voltages associated with performing the memory operation, gating off a current needed for performing the memory operation, and limiting the needed current to a magnitude below the threshold magnitude required for the operation. After disabling the memory operation, a mock current can be generated. The mock current is intended to mimic the current normally expended during the memory operation when not disabled, thereby leading a user to believe that the device is continuing to operate normally even though the memory operation that is being attempted is not actually being performed.

公开(公告)号：US09311981B2

公开(公告)日：2016-04-12

申请号：US13954161

申请日：2013-07-30

申请人： Wonseok Lee ,  Seonghyun Jeon ,  Youngkug Moon ,  Dong Hwi Kim

发明人： Wonseok Lee ,  Seonghyun Jeon ,  Youngkug Moon ,  Dong Hwi Kim

IPC分类号： G11C11/16

CPC分类号： G11C11/1675 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1695

摘要： A semiconductor memory device includes a memory cell array of nonvolatile memory cells having a variable resistance element, and a conductor line array capable of generating a compensation magnetic field for the nonvolatile memory cells. A current driver selectively supplies current to conductive lines, a magnetic field sensor senses an applied external magnetic field and generates external magnetic field information, and a controller controls generation of the compensation magnetic field in response to the external magnetic field information.

摘要翻译： 半导体存储器件包括具有可变电阻元件的非易失性存储单元的存储单元阵列和能够产生用于非易失性存储单元的补偿磁场的导线阵列。 电流驱动器选择性地向导线提供电流，磁场传感器感测施加的外部磁场并产生外部磁场信息，并且控制器响应于外部磁场信息控制补偿磁场的产生。

公开(公告)号：US20160070935A1

公开(公告)日：2016-03-10

申请号：US14942665

申请日：2015-11-16

申请人： Everspin Technologies, Inc.

发明人： Syed M. Alam ,  Thomas Andre

IPC分类号： G06F21/79 ,  G06F3/06

CPC分类号： G06F21/79 ,  G06F3/062 ,  G06F3/0653 ,  G06F3/0679 ,  G06F21/78 ,  G06F21/86 ,  G06F2221/2143 ,  G11C7/24 ,  G11C11/1695

摘要： In response to a tamper-attempt indication, a memory device selectively disables one or more memory operations. Disabling can be accomplished by different techniques, including altering bias voltages associated with performing the memory operation, gating off a current needed for performing the memory operation, and limiting the needed current to a magnitude below the threshold magnitude required for the operation. After disabling the memory operation, a mock current can be generated. The mock current is intended to mimic the current normally expended during the memory operation when not disabled, thereby leading a user to believe that the device is continuing to operate normally even though the memory operation that is being attempted is not actually being performed.

摘要翻译： 响应于篡改尝试指示，存储器设备选择性地禁用一个或多个存储器操作。 禁用可以通过不同的技术实现，包括改变与执行存储器操作相关联的偏置电压，选通执行存储器操作所需的电流，以及将所需电流限制在低于操作所需阈值幅度的幅度。 禁用内存操作后，可以生成模拟电流。 模拟电流旨在模拟在不被禁用时在存储器操作期间通常消耗的电流，从而导致用户认为即使正在尝试的存储器操作实际上不被执行，设备也继续正常地操作。

公开(公告)号：US09135970B2

公开(公告)日：2015-09-15

申请号：US14175337

申请日：2014-02-07

申请人： Everspin Technologies, Inc.

发明人： Chitra K. Subramanian ,  Halbert S. Lin ,  Syed M. Alam ,  Thomas Andre

IPC分类号： G11C11/00 ,  G11C5/14 ,  G11C7/24 ,  G11C13/00 ,  G11C11/16

CPC分类号： G06F21/79 ,  G06F21/60 ,  G11C7/14 ,  G11C7/24 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1695 ,  G11C13/0002 ,  G11C13/004 ,  G11C13/0059 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0073

摘要： A technique for detecting tampering attempts directed at a memory device includes setting each of a plurality of detection memory cells to an initial predetermined state, where corresponding portions of the plurality of detection memory cells are included in each of the arrays of data storage memory cells on the memory device. A plurality of corresponding reference bits on the memory device permanently store information representative of the initial predetermined state of each of the detection memory elements. When a tamper detection check is performed, a comparison between the reference bits and the current state of the detection memory cells is used to determine whether any of the detection memory cells have changed state from their initial predetermined states. Based on the comparison, a tamper detect indication is flagged if a threshold level of change is determined. Once a tampering attempt is detected, responses on the memory device include disabling one or more memory operations and generating a mock current to emulate current expected during normal operation.

摘要翻译： 用于检测针对存储器件的篡改尝试的技术包括将多个检测存储器单元中的每一个设置为初始预定状态，其中多个检测存储器单元的相应部分被包括在每个数据存储单元阵列中 存储设备。 存储器装置上的多个对应的参考位永久地存储表示每个检测存储器元件的初始预定状态的信息。 当执行篡改检测检查时，使用检测存储单元的参考位与当前状态之间的比较来确定检测存储单元中的任何一个是否已经从其初始预定状态改变状态。 基于该比较，如果确定了阈值变化水平，则标记篡改检测指示。 一旦检测到篡改尝试，存储器设备上的响应包括禁用一个或多个存储器操作并产生模拟电流以仿真在正常操作期间预期的电流。

公开(公告)号：US09069719B2

公开(公告)日：2015-06-30

申请号：US13691639

申请日：2012-11-30

申请人： Adrian Ong

发明人： Adrian Ong

IPC分类号： G06F11/00 ,  G06F15/167 ,  G06F11/10 ,  G06F3/06 ,  G06F11/07 ,  G06F12/00 ,  G11C11/16 ,  G06F21/00 ,  G11C13/00

CPC分类号： G06F15/167 ,  G06F3/0601 ,  G06F11/0751 ,  G06F11/0793 ,  G06F11/1008 ,  G06F11/1076 ,  G06F12/00 ,  G06F21/00 ,  G11C11/16 ,  G11C11/1677 ,  G11C11/1695 ,  G11C13/0002

摘要： A smart memory system preferably includes a memory including one or more memory chips, and a processor including one or more memory processor chips. The processor may include a common address/data/control memory bus that is configured to provide an asynchronous handshaking interface between the memory array and the memory processor. The processor can offload error data from the memory chip for analysis, and can store poor retention bit address information for memory refreshing in a non-volatile error retention memory. Program logic can also be included for memory address re-configuration. Power management logic can also be included, which may have a process-voltage-temperature compensation voltage generator for providing stable and constant read currents. An asynchronous handshaking interface is provided between the memory array and the memory processor. Write error tagging and write verification circuits can also be included.

摘要翻译： 智能存储器系统优选地包括包括一个或多个存储器芯片的存储器和包括一个或多个存储器处理器芯片的处理器。 处理器可以包括公共地址/数据/控制存储器总线，其被配置为在存储器阵列和存储器处理器之间提供异步握手接口。 处理器可以从内存芯片卸载错误数据进行分析，并且可以在非易失性错误保留存储器中存储用于内存刷新的差的保留位地址信息。 还可以包括程序逻辑用于存储器地址重新配置。 还可以包括电源管理逻辑，其可以具有用于提供稳定且恒定的读取电流的过程电压 - 温度补偿电压发生器。 在存储器阵列和存储器处理器之间提供异步握手接口。 也可以包括写入错误标记和写入验证电路。

公开(公告)号：US08996888B2

公开(公告)日：2015-03-31

申请号：US13630731

申请日：2012-09-28

申请人： Avalanche Technology, Inc.

发明人： Siamack Nemazie ,  Ngon Van Le

IPC分类号： G06F11/30 ,  G06F21/10

CPC分类号： G06F21/10 ,  G06F12/1441 ,  G06F21/80 ,  G06F2221/2107 ,  G11C11/1675 ,  G11C11/1695 ,  G11C13/0059 ,  G11C14/0081

摘要： A mobile device includes an application processor, an RF modem for connection to cellular networks, wireless device for connection to wireless networks, a display coupled to the application processor, audio devices coupled to the application processor, power management for providing power through a main battery; and charging the battery, a hybrid memory including a magnetic memory, the magnetic memory further including a parameter area configured to store parameters used to authenticate access to certain areas of the main memory, and a parameter memory that maintains a first area, used to store protected zone parameters, and a second area used to store authentication parameters, the protection zone parameters and the authentication parameters being associated with access to the certain areas in the main memory that requires authentication. Upon modification of any of the parameters stored in the parameter memory by a user, a corresponding location of the parameter area of the main memory is also modified.

摘要翻译： 移动设备包括应用处理器，用于连接到蜂窝网络的RF调制解调器，用于连接到无线网络的无线设备，耦合到应用处理器的显示器，耦合到应用处理器的音频设备，用于通过主电池提供电力的电源管理 ; 以及对所述电池充电的混合存储器，包括磁存储器的混合存储器，所述磁存储器还包括参数区域，所述参数区域被配置为存储用于认证访问所述主存储器的某些区域的参数;以及参数存储器，所述参数存储器保持用于存储的第一区域 保护区参数，以及用于存储认证参数的第二区域，保护区参数和认证参数与访问需要认证的主存储器中的某些区域相关联。 在修改由用户存储在参数存储器中的任何参数时，主存储器的参数区域的对应位置也被修改。

公开(公告)号：US20150078073A1

公开(公告)日：2015-03-19

申请号：US14553758

申请日：2014-11-25

申请人： Micron Technology, Inc.

发明人： Jun Liu ,  Gurtej Sandhu

IPC分类号： G11C11/16

CPC分类号： G11C11/1675 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1695 ,  H01L43/02

摘要： Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices include memory cells having two pinned layers and a free layer therebetween. By utilizing two pinned layers, the spin torque effect on the free layer from each of the two pinned layers, respectively, allows the memory cells to be programmed with unidirectional currents.

摘要翻译： 配置为单向编程的自旋扭矩传递磁性随机存取存储器件以及编程这种器件的方法。 这些装置包括具有两个钉扎层和其间的自由层的存储单元。 通过利用两个固定层，分别从两个固定层中的每一个自由层上的自旋转矩效应允许以单向电流编程存储器单元。

公开(公告)号：US20150071431A1

公开(公告)日：2015-03-12

申请号：US14072634

申请日：2013-11-05

申请人： QUALCOMM Incorporated

发明人： Xiaochun Zhu ,  Steven M. Millendorf ,  Xu Guo ,  David M. Jacobson ,  Kangho Lee ,  Seung H. Kang ,  Matthew Michael Nowak

IPC分类号： G11C11/16 ,  H04L9/30

CPC分类号： G11C11/1675 ,  G11C11/161 ,  G11C11/1695 ,  H04L9/0866 ,  H04L9/30 ,  H04L9/3278

摘要： One feature pertains to a method of implementing a physically unclonable function (PUF). The method includes exposing an array of magnetoresistive random access memory (MRAM) cells to an orthogonal external magnetic field. The MRAM cells are each configured to represent one of a first logical state and a second logical state, and the orthogonal external magnetic field is oriented in an orthogonal direction to an easy axis of a free layer of the MRAM cells to place the MRAM cells in a neutral logical state that is not the first logical state or the second logical state. The method further includes removing the orthogonal external magnetic field to place each of the MRAM cells of the array randomly in either the first logical state or the second logical state.

摘要翻译： 一个特征涉及实现物理不可克隆功能（PUF）的方法。 该方法包括将磁阻随机存取存储器（MRAM）阵列阵列暴露于正交外部磁场。 MRAM单元各自被配置为表示第一逻辑状态和第二逻辑状态之一，并且正交外部磁场定向为与MRAM单元的自由层的容易轴正交的方向，以将MRAM单元置于 不是第一逻辑状态或第二逻辑状态的中性逻辑状态。 该方法还包括去除正交的外部磁场，将阵列的每个MRAM单元随机地置于第一逻辑状态或第二逻辑状态中。